Manuel Drehwald b7c63a973f add autodiff batching backend

2025-04-04 14:24:23 -04:00

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Auto merge of #133250 - DianQK:embed-bitcode-pgo, r=nikic

2025-03-01 08:22:18 +00:00

builder

add autodiff batching backend

2025-04-04 14:24:23 -04:00

coverageinfo

coverage: Convert and check span coordinates without a local file ID

2025-03-20 13:29:32 +11:00

debuginfo

Create a safe wrapper around LLVMRustDIBuilderCreateMemberType

2025-03-18 17:15:02 +00:00

llvm

add autodiff batching backend

2025-04-04 14:24:23 -04:00

abi.rs

Remove an unused lifetime param

2025-02-24 15:11:29 +00:00

allocator.rs

Remove implicit #[no_mangle] for #[rustc_std_internal_symbol]

2025-03-17 14:08:09 +00:00

asm.rs

Rollup merge of #137549 - oli-obk:llvm-ffi, r=davidtwco

2025-03-07 19:15:34 +01:00

attributes.rs

Rename OptimizeAttr::None to Default

2025-01-24 19:34:01 +00:00

base.rs

Add new_regular and new_allocator to ModuleCodegen

2025-02-23 21:23:38 +08:00

builder.rs

Rollup merge of #137549 - oli-obk:llvm-ffi, r=davidtwco

2025-03-07 19:15:34 +01:00

callee.rs

Merge two operations that were always performed together

2025-02-20 11:24:00 +00:00

common.rs

Rollup merge of #137549 - oli-obk:llvm-ffi, r=davidtwco

2025-03-07 19:15:34 +01:00

consts.rs

add autodiff batching backend

2025-04-04 14:24:23 -04:00

context.rs

add autodiff batching backend

2025-04-04 14:24:23 -04:00

declare.rs

Make allocator shim creation mostly use safe code

2025-02-24 15:11:29 +00:00

errors.rs

update autodiff flags

2025-02-21 21:51:20 -05:00

intrinsic.rs

Remove implicit #[no_mangle] for #[rustc_std_internal_symbol]

2025-03-17 14:08:09 +00:00

lib.rs

Rollup merge of #138331 - nnethercote:use-RUSTC_LINT_FLAGS-more, r=onur-ozkan,jieyouxu

2025-03-12 17:59:08 +01:00

llvm_util.rs

Remove out of date comment.

2025-03-05 09:52:28 +11:00

mono_item.rs

Merge two operations that were always performed together

2025-02-20 11:24:00 +00:00

type_.rs

Generalize BaseTypeCodegenMethods

2025-02-24 15:11:29 +00:00

type_of.rs

rename BackendRepr::Vector → SimdVector

2025-02-28 17:17:45 +01:00

va_arg.rs

Teach rust core about Xtensa VaListImpl and add a custom lowering of vaarg for xtensa.

2024-12-03 10:54:08 +00:00

value.rs

Add warn(unreachable_pub) to rustc_codegen_llvm.

2024-08-16 08:46:57 +10:00