Tsukasa OI 5c0c7ac77c RISC-V: tidying: Make auxvec-based enablement a block ...

Because this function will be no longer auxvec-only, this commit adds a
comment to mark auxvec-based part.

It *does not* add a comment to "base ISA" part because it may also use
`riscv_hwprobe`-based results.

2025-04-16 00:56:48 +00:00

..

detect

RISC-V: tidying: Make auxvec-based enablement a block

2025-04-16 00:56:48 +00:00

lib.rs

Remove some allow(unsafe_op_in_unsafe_fn)s and use target_feature 1.1 in examples

2025-02-25 01:11:47 +00:00