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rust/tests/ui/check-cfg/target_feature.stderr
Stuart Cook 6aec7de700 Rollup merge of #138823 - a4lg:riscv-feature-addition-base-i, r=Amanieu 
rustc_target: RISC-V: add base `I`-related important extensions

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

*   Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or
*   Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and
*   Available on LLVM 18.

This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications).

LLVM Definitions:

*   [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137)
*   [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120)
*   [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124)
*   [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155)
*   [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144)

Additional (1):
One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`.

Additional (2):
In RISC-V, `G` is an abbreviation of following extensions:
*   `I`
*   `M`
*   `A`
*   `F`
*   `D`
*   `Zicsr` (although implied by `F`)
*   `Zifencei`

and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though).

--------

This is the version 4.
`Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`).

Version 4:
*   Fixed some commit messages,
*   Added Android / VxWorks targets to imply `G` and
*   Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`)
    since #138742 is now merged.

Related:
*   #44839
    (`riscv_target_feature`)
*   #114544
    (This PR can be a prerequisite of resolving a part of that tracking issue)
*   #138742
    (Touches the same place and vector extensions depend on `Zicsr`)

NOT Related but linked:
*   #132618
    (This PR won't be blocked by this issue since none of those extensions do not change the ABI)

`@rustbot` r? `@Amanieu`
`@rustbot` label +T-compiler +O-riscv +A-target-feature
2025-04-02 13:10:37 +11:00

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warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
--> $DIR/target_feature.rs:16:10
|
LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
= note: expected values for `target_feature` are: `10e60`
`2e3`
`3e3r1`
`3e3r2`
`3e3r3`
`3e7`
`7e10`
`a`
`aclass`
`adx`
`aes`
`altivec`
`alu32`
`amx-avx512`
`amx-bf16`
`amx-complex`
`amx-fp16`
`amx-fp8`
`amx-int8`
`amx-movrs`
`amx-tf32`
`amx-tile`
`amx-transpose`
`atomics`
`avx`
`avx2`
`avx512bf16`
`avx512bitalg`
`avx512bw`
`avx512cd`
`avx512dq`
`avx512f`
`avx512fp16`
`avx512ifma`
`avx512vbmi`
`avx512vbmi2`
`avx512vl`
`avx512vnni`
`avx512vp2intersect`
`avx512vpopcntdq`
`avxifma`
`avxneconvert`
`avxvnni`
`avxvnniint16`
`avxvnniint8`
`backchain`
`bf16`
`bmi1`
`bmi2`
`bti`
`bulk-memory`
`c`
`cache`
`cmpxchg16b`
`crc`
`crt-static`
`cssc`
`d`
`d32`
`deflate-conversion`
`dit`
`div32`
`doloop`
`dotprod`
`dpb`
`dpb2`
`dsp`
`dsp1e2`
`dspe60`
`e`
`e1`
`e2`
`ecv`
`edsp`
`elrw`
`enhanced-sort`
`ermsb`
`exception-handling`
`extended-const`
`f`
`f16c`
`f32mm`
`f64mm`
`faminmax`
`fcma`
`fdivdu`
`fhm`
`flagm`
`flagm2`
`float1e2`
`float1e3`
`float3e4`
`float7e60`
`floate1`
`fma`
`fp-armv8`
`fp16`
`fp64`
`fp8`
`fp8dot2`
`fp8dot4`
`fp8fma`
`fpregs`
`fpuv2_df`
`fpuv2_sf`
`fpuv3_df`
`fpuv3_hf`
`fpuv3_hi`
`fpuv3_sf`
`frecipe`
`frintts`
`fxsr`
`gfni`
`guarded-storage`
`hard-float`
`hard-float-abi`
`hard-tp`
`hbc`
`high-registers`
`high-word`
`hvx`
`hvx-length128b`
`hwdiv`
`i8mm`
`isa-68000`
`isa-68010`
`isa-68020`
`isa-68030`
`isa-68040`
`isa-68060`
`isa-68881`
`isa-68882`
`jsconv`
`kl`
`lahfsahf`
`lam-bh`
`lamcas`
`lasx`
`lbt`
`ld-seq-sa`
`leoncasa`
`lor`
`lse`
`lse128`
`lse2`
`lsx`
`lut`
`lvz`
`lzcnt`
`m`
`mclass`
`mops`
`movbe`
`movrs`
`mp`
`mp1e2`
`msa`
`msync`
`mte`
`multivalue`
`mutable-globals`
`neon`
`nnp-assist`
`nontrapping-fptoint`
`nvic`
`paca`
`pacg`
`pan`
`partword-atomics`
`pauth-lr`
`pclmulqdq`
`pmuv3`
`popcnt`
`power10-vector`
`power8-altivec`
`power8-crypto`
`power8-vector`
`power9-altivec`
`power9-vector`
`prfchw`
`quadword-atomics`
`rand`
`ras`
`rclass`
`rcpc`
`rcpc2`
`rcpc3`
`rdm`
`rdrand`
`rdseed`
`reference-types`
`relax`
`relaxed-simd`
`reserve-x18`
`rtm`
`sb`
`scq`
`sha`
`sha2`
`sha3`
`sha512`
`sign-ext`
`simd128`
`sm3`
`sm4`
`sme`
`sme-b16b16`
`sme-f16f16`
`sme-f64f64`
`sme-f8f16`
`sme-f8f32`
`sme-fa64`
`sme-i16i64`
`sme-lutv2`
`sme2`
`sme2p1`
`soft-float`
`spe`
`ssbs`
`sse`
`sse2`
`sse3`
`sse4.1`
`sse4.2`
`sse4a`
`ssse3`
`ssve-fp8dot2`
`ssve-fp8dot4`
`ssve-fp8fma`
`sve`
`sve-b16b16`
`sve2`
`sve2-aes`
`sve2-bitperm`
`sve2-sha3`
`sve2-sm4`
`sve2p1`
`tail-call`
`tbm`
`thumb-mode`
`thumb2`
`tme`
`transactional-execution`
`trust`
`trustzone`
`ual`
`unaligned-scalar-mem`
`unaligned-vector-mem`
`v`
`v5te`
`v6`
`v6k`
`v6t2`
`v7`
`v8`
`v8.1a`
`v8.2a`
`v8.3a`
`v8.4a`
`v8.5a`
`v8.6a`
`v8.7a`
`v8.8a`
`v8.9a`
`v8plus`
`v9`
`v9.1a`
`v9.2a`
`v9.3a`
`v9.4a`
`v9.5a`
`v9a`
`vaes`
`vdsp2e60f`
`vdspv1`
`vdspv2`
`vector`
`vector-enhancements-1`
`vector-enhancements-2`
`vector-packed-decimal`
`vector-packed-decimal-enhancement`
`vector-packed-decimal-enhancement-2`
`vfp2`
`vfp3`
`vfp4`
`vh`
`virt`
`virtualization`
`vpclmulqdq`
`vsx`
`wfxt`
`wide-arithmetic`
`widekl`
`x87`
`xop`
`xsave`
`xsavec`
`xsaveopt`
`xsaves`
`za128rs`
`za64rs`
`zaamo`
`zabha`
`zacas`
`zalrsc`
`zama16b`
`zawrs`
`zba`
`zbb`
`zbc`
`zbkb`
`zbkc`
`zbkx`
`zbs`
`zdinx`
`zfh`
`zfhmin`
`zfinx`
`zhinx`
`zhinxmin`
`zicntr`
`zicsr`
`zifencei`
`zihintpause`
`zihpm`
`zk`
`zkn`
`zknd`
`zkne`
`zknh`
`zkr`
`zks`
`zksed`
`zksh`
`zkt`
`zvbb`
`zvbc`
`zve32f`
`zve32x`
`zve64d`
`zve64f`
`zve64x`
`zvfh`
`zvfhmin`
`zvkb`
`zvkg`
`zvkn`
`zvknc`
`zvkned`
`zvkng`
`zvknha`
`zvknhb`
`zvks`
`zvksc`
`zvksed`
`zvksg`
`zvksh`
`zvkt`
`zvl1024b`
`zvl128b`
`zvl16384b`
`zvl2048b`
`zvl256b`
`zvl32768b`
`zvl32b`
`zvl4096b`
`zvl512b`
`zvl64b`
`zvl65536b`, and `zvl8192b`
= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
= note: `#[warn(unexpected_cfgs)]` on by default
warning: 1 warning emitted
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