bors 4d247ad7d3 Auto merge of #77306 - lcnr:inline-ok, r=eddyb ...

normalize substs while inlining

fixes #68347 or more precisely, this fixes the same ICE in rust analyser as veloren is pinned to a specific nightly
and had an error with the current one.

I didn't look into creating an MVCE here as that seems fairly annoying, will spend a few minutes doing so rn. (failed)

r? `@eddyb` cc `@bjorn3`

2020-10-18 16:10:00 +00:00

..

check_consts

Make impl Trait unstable in all contexts

2020-10-05 21:44:00 -07:00

add_call_guards.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

add_moves_for_packed_drops.rs

Replace (Body, DefId) with Body where possible

2020-10-04 16:07:03 -07:00

add_retag.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

check_const_item_mutation.rs

Take functions by value

2020-10-10 16:19:53 +02:00

check_packed_ref.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

check_unsafety.rs

Change ty.kind to a method

2020-09-04 17:47:51 +02:00

cleanup_post_borrowck.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

const_prop.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

deaggregator.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

dest_prop.rs

Replace (Body, DefId) with Body where possible

2020-10-04 16:07:03 -07:00

dump_mir.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

early_otherwise_branch.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

elaborate_drops.rs

Replace (Body, DefId) with Body where possible

2020-10-04 16:07:03 -07:00

generator.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

inline.rs

Auto merge of #77306 - lcnr:inline-ok, r=eddyb

2020-10-18 16:10:00 +00:00

instcombine.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

instrument_coverage.rs

instrument-coverage: try our best to not ICE

2020-10-16 21:46:41 +03:00

match_branches.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

mod.rs

Remove the old copy propagation pass

2020-10-17 02:25:31 +02:00

multiple_return_terminators.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

no_landing_pads.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

nrvo.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

promote_consts.rs

Create a single source scope for promoteds

2020-10-14 00:00:00 +00:00

remove_noop_landing_pads.rs

Recognize discriminant reads as no-ops in RemoveNoopLandingPads

2020-10-10 00:00:00 +00:00

remove_unneeded_drops.rs

Replace (Body, DefId) with Body where possible

2020-10-04 16:07:03 -07:00

required_consts.rs

mv compiler to compiler/

2020-08-30 18:45:07 +03:00

rustc_peek.rs

Replace (Body, DefId) with Body where possible

2020-10-04 16:07:03 -07:00

simplify_branches.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

simplify_comparison_integral.rs

Use SmallVec in SwitchTargets

2020-10-11 01:14:12 +02:00

simplify_try.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

simplify.rs

Remember the MirSource for each Body

2020-10-04 11:01:38 -07:00

uninhabited_enum_branching.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

unreachable_prop.rs

Refactor how SwitchInt stores jump targets

2020-10-10 17:46:11 +02:00

validate.rs

Validate references to source scopes

2020-10-14 00:00:00 +00:00