sayantn 0ec1d460bb Add the new amx target features

2025-03-05 05:34:37 +05:30

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Auto merge of #133250 - DianQK:embed-bitcode-pgo, r=nikic

2025-03-01 08:22:18 +00:00

builder

update autodiff flags

2025-02-21 21:51:20 -05:00

coverageinfo

coverage: Remove the old code for simplifying counters after MIR opts

2025-02-06 21:44:31 +11:00

debuginfo

Rollup merge of #137210 - workingjubilee:fixup-passmode-import, r=RalfJung

2025-02-19 01:30:12 +01:00

llvm

Revert "Auto merge of #135335 - oli-obk:push-zxwssomxxtnq, r=saethlin"

2025-03-02 18:52:48 +00:00

abi.rs

compiler: Stop reexporting stuff in cg_llvm::abi

2025-02-18 00:31:29 -08:00

allocator.rs

Document some safety constraints and use more safe wrappers

2025-02-11 09:47:13 +00:00

asm.rs

rename BackendRepr::Vector → SimdVector

2025-02-28 17:17:45 +01:00

attributes.rs

Rename OptimizeAttr::None to Default

2025-01-24 19:34:01 +00:00

base.rs

Add new_regular and new_allocator to ModuleCodegen

2025-02-23 21:23:38 +08:00

builder.rs

codegen_llvm: avoid Deref impls w/ extern type

2025-02-24 08:08:55 +00:00

callee.rs

Merge two operations that were always performed together

2025-02-20 11:24:00 +00:00

common.rs

Auto merge of #137959 - matthiaskrgr:rollup-62vjvwr, r=matthiaskrgr

2025-03-04 02:27:56 +00:00

consts.rs

Merge two operations that were always performed together

2025-02-20 11:24:00 +00:00

context.rs

codegen_llvm: avoid Deref impls w/ extern type

2025-02-24 08:08:55 +00:00

declare.rs

compiler: Stop reexporting stuff in cg_llvm::abi

2025-02-18 00:31:29 -08:00

errors.rs

update autodiff flags

2025-02-21 21:51:20 -05:00

intrinsic.rs

rename BackendRepr::Vector → SimdVector

2025-02-28 17:17:45 +01:00

lib.rs

Rollup merge of #137741 - cuviper:const_str-raw_entry, r=Mark-Simulacrum

2025-03-03 10:41:00 +01:00

llvm_util.rs

Add the new amx target features

2025-03-05 05:34:37 +05:30

mono_item.rs

Merge two operations that were always performed together

2025-02-20 11:24:00 +00:00

type_.rs

Rollup merge of #136721 - dpaoliello:cleanllvm2, r=Zalathar

2025-02-11 01:02:40 -05:00

type_of.rs

rename BackendRepr::Vector → SimdVector

2025-02-28 17:17:45 +01:00

va_arg.rs

Teach rust core about Xtensa VaListImpl and add a custom lowering of vaarg for xtensa.

2024-12-03 10:54:08 +00:00

value.rs

Add warn(unreachable_pub) to rustc_codegen_llvm.

2024-08-16 08:46:57 +10:00