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62 Commits

Author SHA1 Message Date
Amanieu d'Antras
644e8f8900 Replace associated const hacks with inline consts 
Fixes #1368
 2023-03-05 18:00:21 +01:00
Ralf Jung
5afa869e0a use inline const for last simd_shuffle argument 2023-01-10 00:23:14 +00:00
Jacob Bramley
665e33f3be Match Neon test features to their intrinsics. 
The tests can run if and only if the target_features for the
corresponding intrinsics are detected at run-time, so make sure that the
tests have an appropriate `simd_test()`.

This fixes some failures due to tests running when they shouldn't. For
example, some tests would fail on hardware that lacks "fcma".
 2023-01-09 15:08:12 +00:00
Jacob Bramley
f966d451b5 Decouple TargetFeature strings. 
"arm" and "aarch64" support different sets of `target_feature` and
`simd_test` arguments, and for "arm", the set of features that can be
dynamically detected is different again. Restructure the generator code
to allow this to be expressed accurately (in future patches).

This implementation preserves the way that target features are specified
for shared intrinsics, because this has an impact on the generated
documentation. In particular, rustdoc cannot look inside
`cfg_attr(target_arch = ...)` tests, so we use unconditional
`target_feature` attributes where possible.
 2023-01-09 15:08:12 +00:00
Amanieu d'Antras
eea72e2ed7 Mark arm_shared intrinsics as stable on all target except ARM (#1345) 2022-10-25 20:18:19 +01:00
Yuri Astrakhan
81c221f058 Edition 2021, apply clippy::uninlined_format_args fix (#1339) 2022-10-25 20:17:23 +01:00
Amanieu d'Antras
e79701c56e Properly fix vext intrinsic tests 
This was previously done as part of #1326, but it modified generated
code without fixing the root issue in neon.spec.
 2022-08-22 23:46:15 +02:00
psvri
8119ecd492 Adding doc links for arm neon intrinsics 2022-08-12 19:51:56 +02:00
Jamie Cunliffe
e75d75e292 Add the rdm target feature to the sqrdmlsh intrinsic. (#1285) 2022-04-08 19:29:11 +01:00
Frank Steffahn
df24e2a0f8 Fix a bunch of typos 2021-12-14 10:17:43 -08:00
Sparrow Li
88e98e9c60 Stabilize armv8 neon instruction set on aarch64 (#1266) 2021-12-13 01:52:20 +00:00
Amanieu d'Antras
937978eeef Update the intrinsic checker tool (#1258) 2021-12-04 13:03:30 +00:00
Sparrow Li
7c3bd04537 complete armv8 instructions (#1256) 2021-11-19 01:24:36 +00:00
Sparrow Li
be5e1be224 Add remaining insturctions (#1250) 
* add vmmla vusmmla vsm4e vsm3 vrax1 vxar vsha512 vbcax veor3 neon instructions

* update runtime feature detect

* correct tests

* add `vrnd32x` `vrnd64x`

* add MISSING.md
 2021-11-10 15:19:59 +00:00
Jamie Cunliffe
8d6f3f36b3 Correct the vqrdmlah intrinsics. (#1246) 2021-11-04 14:16:26 +00:00
Jamie Cunliffe
813530237d Do not emit undefined lshr/ashr for Neon shifts (#1238) 2021-10-22 20:24:54 +01:00
Sparrow Li
9df48f1e57 Complete the remaining neon instructions (#1230) 2021-10-21 10:52:05 +01:00
Sparrow Li
68e35d306f Complete vld* and vst* neon instructions (#1224) 2021-09-29 04:28:10 +01:00
Sparrow Li
bdea403c54 Complete vst1 neon instructions (#1221) 2021-09-24 13:26:29 +01:00
Hans Kratz
504b0cf68b Arm Fused Multiply-Add fixes (#1219) 2021-09-20 17:18:20 +01:00
Sparrow Li
328553ef64 Complete vld1 instructions with some corrections (#1216) 2021-09-18 14:13:24 +01:00
Sparrow Li
9e34c6d4c8 Add vst neon instructions (#1205) 
* add vst neon instructions

* modify the instruction limit
 2021-08-31 21:35:30 +01:00
Sparrow Li
4baf95fddd add vldx neon instructions (#1200) 2021-08-24 19:51:30 +01:00
Adam Gemmell
8cb8cd2142 Replace the crypto feature with aes in generated intrinsics for aarch64 
This allows us to deprecate the crypto target_feature in favour of its
subfeatures.

We cannot do this yet for ARM targets as LLVM requires the crypto
feature. This was fixed in
b8baa2a913
 2021-08-02 23:38:57 +01:00
Ralf Jung
a34883b5d3 manually const-ify shuffle arguments (#1160) 2021-05-11 21:11:52 +01:00
SparrowLii
8a2936b9a2 Completion of vcvt neon instruction 2021-05-07 23:02:39 +01:00
SparrowLii
911ace84b2 Add vqrdmulh, vqrdmlah, vqrdmlsh neon instructions 2021-05-06 15:44:54 +01:00
Sparrow Li
fd29f9602c Add vmul_n, vmul_lane, vmulx neon instructions (#1147) 2021-04-30 21:09:41 +01:00
Sparrow Li
07f1d0cae3 Add vmla_n, vmla_lane, vmls_n, vmls_lane neon instructions (#1145) 2021-04-28 22:59:41 +01:00
Sparrow Li
8852d07441 add vcopy neon instructions (#1139) 2021-04-24 01:49:11 +01:00
Sparrow Li
de3e8f72c5 Add vqdmul* neon instructions (#1130) 2021-04-21 15:27:08 +01:00
Sparrow Li
6354de5993 Add vrshl, vrshr, vrshrn, vrsra, vsra neon instructions (#1127) 2021-04-19 17:49:44 +01:00
Sebastian Thiel
43126c3f65 [DRAFT] intrinsics for all architectures appear in rustdoc (#1104) 2021-04-17 13:46:33 +01:00
Sparrow Li
e792dfd02c add vqshl, vqshrn, vqshrun neon instructions (#1120) 2021-04-16 13:22:39 +01:00
Sparrow Li
23f45cc955 Add vqrsh* neon instructions (#1119) 2021-04-15 12:29:04 +01:00
liushuyu
33afae1df7 aarch64: add uzp1, uzp2 instructions (#1118) 2021-04-15 12:21:31 +01:00
surechen
aaaa9335eb add neon instruction vfma (#1116) 2021-04-14 15:34:53 +01:00
Sparrow Li
88a5de08cb Allow primitive types in the code generator and add vdup instructions (#1114) 2021-04-12 14:08:26 +01:00
Sparrow Li
5ee0274cef add vshl and vshr neon instructions (#1111) 2021-04-09 08:49:23 +01:00
surechen
e6a81b7566 add neon instruction vmaxnm_f* vpmaxnm_f* vminnm_f* vpminnm_f* (#1105) 2021-04-06 06:57:05 +01:00
Sparrow Li
6201670dd2 Enable constant parameters in the code generator and add vext instructions (#1106) 2021-04-02 22:02:22 +01:00
Sparrow Li
7b21d85a41 add vmovn_high, vrbit, vrnd, vsubhn neon instructions (#1103) 2021-03-31 15:48:58 +01:00
Sparrow Li
64f84788c9 add vreinterpret neon instructions (#1101) 2021-03-30 06:51:01 +01:00
SparrowLii
770ced9a69 add vzip1, vzip2 instructions 2021-03-23 05:50:03 +00:00
SparrowLii
91bed9bd0c correct instruction names 2021-03-23 05:50:03 +00:00
SparrowLii
69bb74bca6 add vtrn1 and vtrn2 neon instructions 2021-03-23 05:50:03 +00:00
Sparrow Li
63facc4b68 Add vmull, vmull_high, vmlal, vmlal_high, vmlsl, vmlsl_high neon instructions (#1091) 2021-03-20 22:35:19 +00:00
Sparrow Li
4773f9b1d2 Support three parameters in the code generator and add vmla and vmls instructions (#1088) 2021-03-17 09:34:21 +00:00
Sparrow Li
7accc82569 add vcvt, vcvta, vcvtn, vcvtm, vcvtp neon instructions (#1084) 2021-03-16 14:30:05 +00:00
Sparrow Li
bb84df7d9f implement different types of parameters and double suffixes in code generator (#1083) 2021-03-15 18:45:51 +00:00