Commit Graph

148 Commits

Author SHA1 Message Date
Vadim Petrochenkov
8d5109aa6e compiletest: Support matching on diagnostics without a span 2025-03-25 17:33:09 +03:00
León Orell Valerian Liehr
10055fb03a Rollup merge of #138056 - heiher:loong64v1.1-features, r=petrochenkov
rustc_target: Add target features for LoongArch v1.1

This patch adds new target features for LoongArch v1.1:

* div32
* lam-bh
* lamcas
* ld-seq-sa
* scq
2025-03-15 00:18:22 +01:00
WANG Rui
d989bf5bbe rustc_target: Add target features for LoongArch v1.1 2025-03-14 09:52:02 +08:00
StevenMia
3583554405 chore: Fix some comments
Signed-off-by: StevenMia <flite@foxmail.com>
2025-03-09 18:31:14 +08:00
Taiki Endo
6f7fd11474 rustc_target: Add msync target feature and enable it on powerpcspe targets 2025-03-02 03:03:52 +09:00
David Wood
92eb4450fa tests: use minicore more
minicore makes it much easier to add new language items to all of the
existing `no_core` tests.
2025-02-24 09:26:54 +00:00
Michael Goulet
828a3a41b3 Rollup merge of #137417 - taiki-e:riscv-atomic, r=Amanieu
rustc_target: Add more RISC-V atomic-related features

This is a continuation of https://github.com/rust-lang/rust/pull/130877 and adds a few target features, including `zacas`, which was experimental in LLVM 19 and marked non-experimental in LLVM 20.

This adds the following target features to unstable riscv_target_feature:

- `za64rs` (Za64rs Extension 1.0): Reservation Set Size of at Most 64 Bytes
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L227-L228), [available since LLVM 18](8649328060))
- `za128rs` (Za128rs Extension 1.0): Reservation Set Size of at Most 128 Bytes
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L230-L231), [available since LLVM 18](8649328060))
  - IIUC, `za*rs` can be referenced when implementing helpers to reduce contention in synchronization primitives, like [`crossbeam_utils::CachePadded`](https://docs.rs/crossbeam-utils/latest/crossbeam_utils/struct.CachePadded.html). (relevant discussion: https://github.com/riscv/riscv-profiles/issues/79)
- `zacas` (Zacas Extension 1.0): Atomic Compare-And-Swap Instructions (`amocas.{w,d,q}{,.aq,.rl,.aqrl}` and `amocas.{b,h}{,.aq,.rl,.aqrl}` when `zabha` is also enabled)
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L240-L243), [available as non-experimental since LLVM 20](614aeda93b))
  - This implies `zaamo`.
  - This is used to optimize CAS in existing atomics and/or implement 64-bit/128-bit atomics on riscv32/riscv64 (e.g., https://github.com/taiki-e/portable-atomic/pull/173).
  - Note that [LLVM does not automatically use this instruction for 64-bit/128-bit atomics on riscv32/riscv64 even if this feature is enabled, because doing it changes the ABI](876174ffd7/llvm/docs/RISCVUsage.rst (riscv-zacas-note)). (If the ability to do that is provided by LLVM in the future, it should probably be controlled by another ABI feature similar to `forced-atomics`.)
- `zama16b` (Zama16b Extension 1.0): Atomic 16-byte misaligned loads, stores and AMOs
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L255-L256), [available since LLVM 19](b090569685))
  - IIUC, unlike AArch64 FEAT_LSE2 which also makes 16-byte aligned ldp ({i,u}128 load) atomic, this extension only affects instructions that already considered atomic if they were naturally aligned. i.e., fld (f64 load) on riscv32 would not be atomic with or without this extension ([relevant QEMU code](b69801dd6b/target/riscv/insn_trans/trans_rvd.c.inc (L50-L62))).
- `zawrs` (Zawrs Extension 1.0): Wait on Reservation Set (`wrs.nto` and `wrs.sto`)
  ([definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0-rc2/llvm/lib/Target/RISCV/RISCVFeatures.td#L258), [available as non-experimental since LLVM 17](d41a73aa94))
  - This is used to optimize synchronization primitives (e.g., Linux uses this for spinlocks (b8ddb0df30)).

Btw, the question of whether `zaamo` is implied by `zabha` or not, which was discussed in https://github.com/rust-lang/rust/pull/130877, has been resolved in LLVM 20, since LLVM now treats `zaamo` as implied by `zabha`/`zacas` (https://github.com/llvm/llvm-project/pull/115694), just like GCC and rustc.

r? `@Amanieu`

`@rustbot` label +O-riscv +A-target-feature
2025-02-24 19:21:47 -05:00
Taiki Endo
a343dcb97f rustc_target: Add more RISC-V atomic-related features 2025-02-22 16:15:14 +09:00
Folkert de Vries
69c7e1d02f add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.

There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):

- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.

And then there are a number of facilities without any implied target features

- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.

The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](d49a2d2bc9/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-02-21 00:26:30 +01:00
Michael Goulet
6d71251cf9 Trim suggestion parts to the subset that is purely additive 2025-02-14 00:44:10 -08:00
Michael Goulet
b480a9214a Use underline suggestions for purely 'additive' replacements 2025-02-14 00:27:13 -08:00
Jacob Pratt
6f671ad6c3 Rollup merge of #134999 - Berrysoft:dev/new-cygwin-target, r=chenyukang,workingjubilee
Add cygwin target.

This PR simply adds cygwin target together with msys2 target, based on ````@ookiineko```` 's (the account has been deleted) [work](https://github.com/ookiineko-cygport/rust) on cygwin target. My full work is here: https://github.com/rust-lang/rust/compare/master...Berrysoft:rust:dev/cygwin

I have succeeded in building a new rustc for cygwin target, and eventually distributed a new version of [fish-shell](https://github.com/Berrysoft/fish-shell/releases) (rewritten by Rust) for MSYS2.

I will open a new PR to fix std if this PR is accepted.
2025-02-13 03:53:28 -05:00
Esteban Küber
f0845adb0c Show diff suggestion format on verbose replacement
```
error[E0610]: `{integer}` is a primitive type and therefore doesn't have fields
  --> $DIR/attempted-access-non-fatal.rs:7:15
   |
LL |     let _ = 2.l;
   |               ^
   |
help: if intended to be a floating point literal, consider adding a `0` after the period and a `f64` suffix
   |
LL -     let _ = 2.l;
LL +     let _ = 2.0f64;
   |
```
2025-02-10 20:21:39 +00:00
王宇逸
f94ada13de Add cygwin target.
Co-authored-by: Ookiineko <chiisaineko@protonmail.com>
Co-authored-by: nora <48135649+Noratrieb@users.noreply.github.com>
Co-authored-by: Jubilee <workingjubilee@gmail.com>
2025-02-10 17:13:15 +08:00
bors
c03c38d5c2 Auto merge of #134740 - Flakebi:amdgpu-target, r=workingjubilee
Add amdgpu target

Add amdgpu target to rustc and enable the LLVM target.

Fix compiling `core` with the amdgpu:
The amdgpu backend makes heavy use of different address spaces. This
leads to situations, where a pointer in one addrspace needs to be casted
to a pointer in a different addrspace. `bitcast` is invalid for this
case, `addrspacecast` needs to be used.

Fix compilation failures that created bitcasts for such cases by
creating pointer casts (which creates an `addrspacecast` under the hood)
instead.

MCP: https://github.com/rust-lang/compiler-team/issues/823
Tracking issue: #135024
Kinda related to the original amdgpu tracking issue #51575 (though that one has been closed for a while).
2025-02-10 05:18:36 +00:00
León Orell Valerian Liehr
d81701b610 Rollup merge of #128045 - pnkfelix:rustc-contracts, r=oli-obk
#[contracts::requires(...)]  + #[contracts::ensures(...)]

cc https://github.com/rust-lang/rust/issues/128044

Updated contract support: attribute syntax for preconditions and postconditions, implemented via a series of desugarings  that culminates in:
1. a compile-time flag (`-Z contract-checks`) that, similar to `-Z ub-checks`, attempts to ensure that the decision of enabling/disabling contract checks is delayed until the end user program is compiled,
2. invocations of lang-items that handle invoking the precondition,  building a checker for the post-condition, and invoking that post-condition checker at the return sites for the function, and
3. intrinsics for the actual evaluation of pre- and post-condition predicates that third-party verification tools can intercept and reinterpret for their own purposes (e.g. creating shims of behavior that abstract away the function body and replace it solely with the pre- and post-conditions).

Known issues:

 * My original intent, as described in the MCP (https://github.com/rust-lang/compiler-team/issues/759) was   to have a rustc-prefixed attribute namespace (like   rustc_contracts::requires). But I could not get things working when I tried   to do rewriting via a rustc-prefixed builtin attribute-macro. So for now it  is called `contracts::requires`.

 * Our attribute macro machinery does not provide direct support for attribute arguments that are parsed like rust expressions. I spent some time trying to add that (e.g. something that would parse the attribute arguments as an AST while treating the remainder of the items as a token-tree), but its too big a lift for me to undertake. So instead I hacked in something approximating that goal, by semi-trivially desugaring the token-tree attribute contents into internal AST constucts. This may be too fragile for the long-term.
   * (In particular, it *definitely* breaks when you try to add a contract to a function like this: `fn foo1(x: i32) -> S<{ 23 }> { ... }`, because its token-tree based search for where to inject the internal AST constructs cannot immediately see that the `{ 23 }` is within a generics list. I think we can live for this for the short-term, i.e. land the work, and continue working on it while in parallel adding a new attribute variant that takes a token-tree attribute alongside an AST annotation, which would completely resolve the issue here.)

* the *intent* of `-Z contract-checks` is that it behaves like `-Z ub-checks`, in that we do not prematurely commit to including or excluding the contract evaluation in upstream crates (most notably, `core` and `std`). But the current test suite does not actually *check* that this is the case. Ideally the test suite would be extended with a multi-crate test that explores the matrix of enabling/disabling contracts on both the upstream lib and final ("leaf") bin crates.
2025-02-05 05:03:01 +01:00
Matthias Krüger
e4eedb5488 Rollup merge of #134814 - sayantn:keylocker, r=oli-obk
Add `kl` and `widekl` target features, and the feature gate

This is an effort towards #134813. This PR adds the target-features and the feature gate to `rustc`

<!--
```@rustbot``` label O-x86_64 O-x86_32 A-target-feature
r? compiler
-->
2025-02-04 06:13:58 +01:00
Celina G. Val
2c4923e6bc Update test output to include check_contracts cfg
This is now a valid expected value.
2025-02-03 13:55:15 -08:00
Flakebi
56795fb77a Add amdgpu target
Add target and compile the amdgpu llvm backend.
2025-01-31 09:59:41 +01:00
Jacob Pratt
cecdb32d0f Rollup merge of #134358 - workingjubilee:configure-my-riscv-abi, r=fmease
compiler: Set `target_abi = "ilp32e"` on all riscv32e targets

This allows compile-time configuration based on this. In the near future we should do this across all RISCV targets, probably, but this cfg is essential for building software usable on these targets, and they are tier 3 so it seems less of a concern to tweak their definition thusly.
2025-01-26 01:51:15 -05:00
Jacob Pratt
0d0e841594 Rollup merge of #133631 - flba-eb:add_nto_qnx71_iosock_support, r=workingjubilee
Support QNX 7.1 with `io-sock`+libstd and QNX 8.0 (`no_std` only)

Changes of this pull request:

1. Refactor code for qnx nto targets to share more code in file `nto_qnx.rs`
1. Add support for an additional network stack on nto qnx 7.1.

   QNX 7.1 supports two network stacks:

   1. `io-pkt`, which is default
   2. `io-sock`, which is optional on 7.1 but default in QNX 8.0

   As one can see in the [io-sock migration notes](https://www.qnx.com/developers/docs/7.1/index.html#com.qnx.doc.neutrino.io_sock/topic/migrate_app.html), this changes the libc API in a way similar to e.g. linux-gnu vs. linux-musl.

   This change adds a new target which has a different value for `target_env`, so that e.g. libc can distinguish between both APIs.

2. Add initial support for QNX 8.0, thanks to AkhilTThomas. As it turned out, the problem with forking many processes still exists in QNX 8.0. Because if this, we are now using it for any QNX version (i.e. not check for `target_env` anymore).
2025-01-26 01:51:14 -05:00
Urgau
c5ea75a5df Filter well known names from check-cfg diagnostics 2025-01-25 12:27:33 +01:00
Urgau
c08cc61bdd Improve check-cfg allow-same-level test
https://github.com/rust-lang/rust/issues/135995
2025-01-24 18:27:08 +01:00
AkhilTThomas
3f045c9d2e add nto80 x86-64 and aarch64 target
Signed-off-by: Florian Bartels <Florian.Bartels@elektrobit.com>
2025-01-24 12:41:49 +00:00
Florian Bartels
84c80151cf Add new target for supporting Neutrino QNX 6.1 with io-socket network stack on aarch64
Signed-off-by: Florian Bartels <Florian.Bartels@elektrobit.com>
2025-01-24 12:32:07 +00:00
Ralf Jung
427abb69bf arm: add unstable soft-float target feature 2025-01-07 16:13:43 +01:00
Sayantan Chakraborty
dc49fdd225 Add kl and widekl target features, and the feature gate 2025-01-06 11:16:24 +05:30
YunQiang Su
51dc350178 fix tests 2025-01-05 13:00:26 +08:00
YunQiang Su
5a0ce36232 Target: Add mips mti baremetal support
Do the same thing as gcc, which use the vendor `mti` to mark
the toolchain as MIPS32r2 default.

We support both big endian and little endian flavor:
  mips-mti-none-elf
  mipsel-mti-none-elf
2025-01-03 22:23:49 +08:00
Urgau
e8a4792b3e Make the test cfg a "userspace" check-cfg 2025-01-02 16:49:55 +01:00
Zalathar
835fbcbcab Remove the -test suffix from normalize directives 2024-12-27 19:58:16 +11:00
Anton Lazarev
e9df8216d5 spell "referring" correctly 2024-12-15 19:36:35 -08:00
Jubilee Young
9a81dc97fb compiler: Set target_abi = "ilp32e" on all riscv32e targets
This allows compile-time configuration based on this.
In the near future we should do this across all RISCV targets, probably,
but this cfg is essential for building software usable on these targets.
2024-12-15 18:42:46 -08:00
许杰友 Jieyou Xu (Joe)
56545cae69 Rollup merge of #134339 - Urgau:tcx-in-early-diag, r=jieyouxu
Pass `TyCtxt` to early diagostics decoration

This PR pass a `TyCtxt` to the early diagnostics decoration code so that diagnostics code that take advantage of (a very limited but still useful) `TyCtxt` in their note, help, suggestions, ...

This is particulary useful for #133221 which wants to get the crate name of a `DefId`, which is possible with `tcx.crate_name(...)`.

I highly recommend reviewing this PR commit by commit.

r? `@jieyouxu`
2024-12-16 01:52:23 +08:00
Urgau
291c519c69 Improve check-cfg Cargo macro diagnostic with crate name 2024-12-15 17:16:01 +01:00
Taiki Endo
56b8e66c66 Add m68k_target_feature 2024-12-15 15:26:50 +09:00
Matthias Krüger
f96fdab101 Rollup merge of #133221 - Urgau:check-cfg-macro-diag, r=jieyouxu
Add external macros specific diagnostics for check-cfg

This PR adds specific check-cfg diagnostics for unexpected cfg in external macros.

As well as hiding the some of the Cargo specific help/suggestions as they distraction for external macros and are generally not the right solution.

Follow-up to #132577

`@rustbot` label +L-unexpected_cfgs
r? compiler
2024-12-14 14:07:56 +01:00
Ralf Jung
d6ddc73dae forbid toggling x87 and fpregs on hard-float targets 2024-12-11 22:18:50 +01:00
Sayantan Chakraborty
1220f393cc Add the power8-crypto target feature 2024-12-09 00:41:35 +05:30
Urgau
43bed16b8b Reduce conflicts for check-cfg target_feature cfg values 2024-12-02 18:22:55 +01:00
Urgau
85e476556b Add specific test for check-cfg "and X more" diagnostic 2024-12-01 20:51:52 +01:00
Taiki Endo
687dc19cb6 Fix handling of x18 in AArch64 inline assembly on ohos/trusty or with -Zfixed-x18 2024-11-26 03:10:22 +09:00
Urgau
e2fbeec150 Add external macro specific diagnostic to check-cfg 2024-11-19 23:09:58 +01:00
Urgau
0ab3ae81a5 Disable most Cargo check-cfg help in external macros 2024-11-19 22:48:36 +01:00
Urgau
44c166e9ac Add Cargo revision and values to the check-cfg macro test 2024-11-19 22:48:36 +01:00
Urgau
cc48194baf Report unexpected_cfgs lint in external macros 2024-11-18 18:52:27 +01:00
Alex Crichton
3af91a4cd4 Stabilize WebAssembly multivalue, reference-types, and tail-call target features
For the `multivalue` and `reference-types` features this commit is
similar to #117457 in that it's stabilizing target features specific to
WebAssembly targets. The previous PR left out these two features because
they weren't expected to change much about compiled code so it was
unclear what the rationale was. It has [since been discovered][blog]
that `reference-types` can be useful as it changes the binary format of
the `call_indirect` instruction. Additionally [on Zulip][zulip] there's
a use case of detecting these features at compile time and generating a
compile error to better warn users about features not supported on
engines.

This PR then additionally adds the `tail-call` feature which corresponds
to the [tail-call] proposal to WebAssembly. This feature advanced to
"phase 4" in the WebAssembly CG awhile back and has been supported in
LLVM for quite some time now. Engines are finishing up implementations
or have already shipped implementations, so while this is a bit of a
late addition to Rust itself it reflects the current status of
WebAssembly's state of the feature.

A test has been added here not only for these features but other
WebAssembly features as well to showcase that they're usable without
feature gates in stable Rust.

[blog]: https://blog.rust-lang.org/2024/09/24/webassembly-targets-change-in-default-target-features.html
[zulip]: https://rust-lang.zulipchat.com/#narrow/stream/122651-general/topic/wasm32.20reference-types.20.2F.20multivalue.20in.201.2E82-beta.20not.20enabled/near/473893987
[tail-call]: https://github.com/webassembly/tail-call
2024-11-10 07:45:14 -08:00
Taiki Endo
c059eb7750 Add v8plus target feature to sparc and use it in create_object_file 2024-11-09 03:22:09 +09:00
Taiki Endo
400a690b5f Add v9 and leoncasa target feature to sparc 2024-11-09 03:17:24 +09:00
Matthias Krüger
088e698835 Rollup merge of #132077 - alexcrichton:wide-arithmetic, r=jieyouxu
Add a new `wide-arithmetic` feature for WebAssembly

This commit adds a new rustc target feature named `wide-arithmetic` for WebAssembly targets. This corresponds to the [wide-arithmetic] proposal for WebAssembly which adds new instructions catered towards accelerating integer arithmetic larger than 64-bits. This proposal to WebAssembly is not standard yet so this new feature is flagged as an unstable target feature. Additionally Rust's LLVM version doesn't support this new feature yet since support will first be added in LLVM 20, so the feature filtering logic for LLVM is updated to handle this.

I'll also note that I'm not currently planning to add wasm-specific intrinsics to `std::arch::wasm32` at this time. The currently proposed instructions are all accessible through `i128` or `u128`-based operations which Rust already supports, so intrinsic shouldn't be necessary to get access to these new instructions.

[wide-arithmetic]: https://github.com/WebAssembly/wide-arithmetic
2024-11-05 23:43:57 +01:00