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58 Commits

Author SHA1 Message Date
Adam Gemmell
8cb8cd2142 Replace the crypto feature with aes in generated intrinsics for aarch64 
This allows us to deprecate the crypto target_feature in favour of its
subfeatures.

We cannot do this yet for ARM targets as LLVM requires the crypto
feature. This was fixed in
b8baa2a913
 2021-08-02 23:38:57 +01:00
Sparrow Li
10f7ebc387 Add vfma and vfms neon instructions (#1169) 2021-05-21 12:26:21 +01:00
Sparrow Li
15749b0ed3 Modify the implementation of d_s64 suffix instructions (#1167) 2021-05-19 03:43:53 +01:00
Sparrow Li
09a05e02f4 Add vmull_p64 and vmull_high_p64 for aarch64 (#1157) 2021-05-15 21:58:23 +01:00
Sparrow Li
4a21f4db0e Add vqmovn neon instructions (#1163) 2021-05-14 12:32:58 +01:00
Ralf Jung
a34883b5d3 manually const-ify shuffle arguments (#1160) 2021-05-11 21:11:52 +01:00
SparrowLii
7516a80c31 Add vset neon instructions 2021-05-11 13:38:16 +01:00
SparrowLii
8a2936b9a2 Completion of vcvt neon instruction 2021-05-07 23:02:39 +01:00
SparrowLii
911ace84b2 Add vqrdmulh, vqrdmlah, vqrdmlsh neon instructions 2021-05-06 15:44:54 +01:00
Sparrow Li
fd29f9602c Add vmul_n, vmul_lane, vmulx neon instructions (#1147) 2021-04-30 21:09:41 +01:00
Sparrow Li
07f1d0cae3 Add vmla_n, vmla_lane, vmls_n, vmls_lane neon instructions (#1145) 2021-04-28 22:59:41 +01:00
Sparrow Li
8852d07441 add vcopy neon instructions (#1139) 2021-04-24 01:49:11 +01:00
Christopher Serr
a43f92a181 Add vrndn neon instructions (#1086) 
This adds the neon instructions for lane-wise rounding without actually
converting the lanes to integers.
 2021-04-22 06:08:40 +01:00
Sparrow Li
de3e8f72c5 Add vqdmul* neon instructions (#1130) 2021-04-21 15:27:08 +01:00
surechen
20c0120362 add neon instruction vaddlv_* (#1129) 2021-04-20 15:19:04 +01:00
Sparrow Li
6354de5993 Add vrshl, vrshr, vrshrn, vrsra, vsra neon instructions (#1127) 2021-04-19 17:49:44 +01:00
surechen
d46e0086e4 add neon instruction vfma_n_* (#1122) 2021-04-17 17:45:54 +01:00
Sebastian Thiel
43126c3f65 [DRAFT] intrinsics for all architectures appear in rustdoc (#1104) 2021-04-17 13:46:33 +01:00
Sparrow Li
e792dfd02c add vqshl, vqshrn, vqshrun neon instructions (#1120) 2021-04-16 13:22:39 +01:00
Sparrow Li
23f45cc955 Add vqrsh* neon instructions (#1119) 2021-04-15 12:29:04 +01:00
liushuyu
33afae1df7 aarch64: add uzp1, uzp2 instructions (#1118) 2021-04-15 12:21:31 +01:00
surechen
aaaa9335eb add neon instruction vfma (#1116) 2021-04-14 15:34:53 +01:00
Sparrow Li
88a5de08cb Allow primitive types in the code generator and add vdup instructions (#1114) 2021-04-12 14:08:26 +01:00
Sparrow Li
5ee0274cef add vshl and vshr neon instructions (#1111) 2021-04-09 08:49:23 +01:00
surechen
a3b5ef2b0c add neon instruction vsubw_* and vsubl_* (#1112) 2021-04-08 15:22:35 +01:00
surechen
e6a81b7566 add neon instruction vmaxnm_f* vpmaxnm_f* vminnm_f* vpminnm_f* (#1105) 2021-04-06 06:57:05 +01:00
Sparrow Li
6201670dd2 Enable constant parameters in the code generator and add vext instructions (#1106) 2021-04-02 22:02:22 +01:00
Sparrow Li
7b21d85a41 add vmovn_high, vrbit, vrnd, vsubhn neon instructions (#1103) 2021-03-31 15:48:58 +01:00
surechen
ef9ec33482 add support for neon instruction vqabs_* (#1102) 2021-03-30 12:22:38 +01:00
Sparrow Li
64f84788c9 add vreinterpret neon instructions (#1101) 2021-03-30 06:51:01 +01:00
surechen
f9e5dfdd66 support neon instruction vabdl_* and vabdl_high_* (#1100) 2021-03-29 11:17:36 +01:00
Sparrow Li
e83d05a3c0 add simd_neg platform intrinsic and vneg, vqneg neon instructions (#1099) 2021-03-29 03:43:36 +01:00
surechen
182d7593f4 support for neon instructions vabal_* and vabal_high_* (#1097) 2021-03-27 16:28:36 +00:00
SparrowLii
770ced9a69 add vzip1, vzip2 instructions 2021-03-23 05:50:03 +00:00
SparrowLii
91bed9bd0c correct instruction names 2021-03-23 05:50:03 +00:00
SparrowLii
69bb74bca6 add vtrn1 and vtrn2 neon instructions 2021-03-23 05:50:03 +00:00
Sparrow Li
63facc4b68 Add vmull, vmull_high, vmlal, vmlal_high, vmlsl, vmlsl_high neon instructions (#1091) 2021-03-20 22:35:19 +00:00
surechen
ce1027d7d5 support s64|u64 for neon instruction vqadd and vqsub (#1090) 2021-03-20 00:55:11 +00:00
Sparrow Li
4773f9b1d2 Support three parameters in the code generator and add vmla and vmls instructions (#1088) 2021-03-17 09:34:21 +00:00
Sparrow Li
7accc82569 add vcvt, vcvta, vcvtn, vcvtm, vcvtp neon instructions (#1084) 2021-03-16 14:30:05 +00:00
Sparrow Li
bb84df7d9f implement different types of parameters and double suffixes in code generator (#1083) 2021-03-15 18:45:51 +00:00
Sparrow Li
01c99c1d05 add vcls, vclz, vcagt, vcage, vcalt, vcale neon instructions (#1072) 2021-03-13 21:55:24 +00:00
Christopher Serr
b132a5c769 Add vrecpe neon instruction (#1079) 
This adds the vector instructions for calculating the lane-wise
reciprocal estimate.
 2021-03-13 17:43:35 +00:00
Christopher Serr
282cfa4db7 Add sqrt and more rsqrte neon instructions (#1078) 
This adds instructions for sqrt and some of the missing reciprocal
square-root estimate instructions.
 2021-03-13 14:27:44 +00:00
Christopher Serr
677644afb9 Add vdiv neon instructions (#1077) 2021-03-13 14:26:44 +00:00
Sparrow Li
088067dbd9 Support _p8 type in stdarch-gen (#1070) 2021-03-10 09:54:43 +00:00
Sparrow Li
7bc90053fd add vcgez, vcgtz, vclez, vcltz neon instructions (#1069) 2021-03-10 06:14:03 +00:00
Sparrow Li
b042298bc4 Modify stdarch-gen to generate instructions composed of multiple functions and add vtst instructions (#1063) 2021-03-08 11:15:04 +00:00
surechen
0203e47f5e support instructions : vabd vaba (#1053) 2021-03-06 17:12:49 +00:00
surechen
a310df2e2c remove redundant code 2021-03-06 17:10:52 +00:00