Commit Graph

44841 Commits

Author SHA1 Message Date
David Tenty
a9cb2d6709 Add a comment 2024-11-29 16:40:13 -05:00
Orion Gonzalez
ce98bf3d79 simplify how the hir_typeck_pass_to_variadic_function diagnostic is created 2024-11-29 20:49:06 +01:00
Maybe Lapkin
144d6cc65b simplify things using tcx.as_lang_item 2024-11-29 20:28:02 +01:00
Maybe Lapkin
c6454dd582 don't polymorphize without a reason to 2024-11-29 20:27:24 +01:00
Maybe Lapkin
ef5808a035 add a fixme for tailcalls with opaque types 2024-11-29 20:26:30 +01:00
Maybe Lapkin
d93ea6bc79 simplify things by using tcx.fn_trait_kind_from_def_id 2024-11-29 20:25:57 +01:00
lcnr
3465ce5786 fast reject: limit recursion depth 2024-11-29 18:01:21 +01:00
Matthias Krüger
eabe6db9b1 Rollup merge of #133592 - WaffleLapkin:misc-meowing, r=jieyouxu
Misc: better instructions for envrc, ignore `/build` instead of `build/`

See commits for more information.

r? ``@jieyouxu``
2024-11-29 16:02:24 +01:00
Matthias Krüger
6c9e922685 Rollup merge of #131323 - jfrimmel:avr-inline-asm-clobber-abi, r=Amanieu
Support `clobber_abi` in AVR inline assembly

This PR implements the `clobber_abi` part necessary to eventually stabilize the inline assembly for AVR. This is tracked in #93335.
This is heavily inspired by the sibling-PR #131310 for the MSP430. I've explained my reasoning in the first commit message in detail, which is reproduced below for easier reviewing:

This follows the [ABI documentation] of AVR-GCC:

> The [...] call-clobbered general purpose registers (GPRs) are registers that might be destroyed (clobbered) by a function call.
>
> - **R18–R27, R30, R31**
>
>   These GPRs are call clobbered. An ordinary function may use them without restoring the contents. [...]
>
> - **R0, T-Flag**
>
>   The temporary register and the T-flag in SREG are also call-clobbered, but this knowledge is not exposed explicitly to the compiler (R0 is a fixed register).

Therefore this commit lists the aforementioned registers `r18–r27`, `r30` and `r31` as clobbered registers. Since the `r0` register (listed above as well) is not available in inline assembly at all (potentially because the AVR-GCC considers it a fixed register causing the register to never be used in register allocation and LLVM adopting this), there is no need to list it in the clobber list (the `r0`-variant is not even available). A comment was added to ensure, that the `r0` gets added to the clobber-list once the register gets usable in inline ASM.
Since the SREG is normally considered clobbered anyways (unless the user supplies the `preserve_flags`-option), there is no need to explicitly list a bit in this register (which is not possible to list anyways).

Note, that this commit completely ignores the case of interrupts (that are described in the ABI-specification), since every register touched in an ISR need to be saved anyways.

[ABI documentation]: https://gcc.gnu.org/wiki/avr-gcc#Call-Used_Registers

r? ``@Amanieu``

``@rustbot`` label +O-AVR
2024-11-29 16:02:20 +01:00
Zalathar
6fc0fe76e8 coverage: Use a query to identify which counter/expression IDs are used 2024-11-30 00:58:48 +11:00
Zalathar
121a17ccc3 coverage: All counter terms in an unused function are zero
This is currently handled automatically by the fact that codegen doesn't visit
coverage statements in unused functions, but that will no longer be the case
when unused IDs are identified by a separate query instead.
2024-11-30 00:54:53 +11:00
Zalathar
05d95a9841 coverage: Allow niches in counter/expression IDs
There is unlikely to be any practical difference between a counter limit of
2^32 and a counter limit of (2^32 - 256).
2024-11-30 00:54:53 +11:00
Zalathar
58e122fef8 coverage: Hoist and explain the check for coverage_cx 2024-11-30 00:54:53 +11:00
Zalathar
3f65114ffc coverage: Rename CrateCoverageContext to CguCoverageContext
This context is stored in `CodegenCx`, which makes it per-CGU rather than
per-crate. A single crate can have multiple CGUs.
2024-11-30 00:54:53 +11:00
bors
0c4f3a45b8 Auto merge of #133619 - matthiaskrgr:rollup-7ywaheb, r=matthiaskrgr
Rollup of 7 pull requests

Successful merges:

 - #132782 (improvements on initial sysroot and libdir finding logics)
 - #133466 (Fix typos in pin.rs)
 - #133492 (bootstrap: allow skipping steps with start of path)
 - #133501 (support revealing defined opaque post borrowck)
 - #133530 (Use consistent wording in docs, use is zero instead of is 0)
 - #133538 (Better diagnostic for fn items in variadic functions)
 - #133590 (Rename `-Zparse-only`)

r? `@ghost`
`@rustbot` modify labels: rollup
2024-11-29 12:05:41 +00:00
lcnr
de94536553 check local cache even if global is usable
we store overflow errors locally, even if we can otherwise
use the global cache for this goal.
2024-11-29 12:44:01 +01:00
Matthias Krüger
ce52b7b3d8 Rollup merge of #133590 - nnethercote:rename-parse-only, r=estebank
Rename `-Zparse-only`

It's a misleading name.

r? ````@estebank````
2024-11-29 10:19:00 +01:00
Matthias Krüger
72cf40d9ed Rollup merge of #133538 - dev-ardi:69232-better-diag, r=compiler-errors
Better diagnostic for fn items in variadic functions

closes #69232
2024-11-29 10:18:59 +01:00
Matthias Krüger
6863327ecc Rollup merge of #133501 - lcnr:post-borrowck-analysis, r=compiler-errors
support revealing defined opaque post borrowck

By adding a new `TypingMode::PostBorrowckAnalysis`. Currently only supported with the new solver and I didn't look into the way we replace `ReErased`. ``@compiler-errors`` mentioned that always using existentials may be unsound.

r? ``@compiler-errors``
2024-11-29 10:18:57 +01:00
bors
5bbbc0938c Auto merge of #133431 - nnethercote:rm-HybridBitSet, r=Mark-Simulacrum
Remove `HybridBitSet`

`HybridBitSet` was introduced under the name `HybridIdxSetBuf` way back in #53383 where it was a big win for NLL borrow checker performance. In #93984 the more flexible `ChunkedBitSet` was added. Uses of `HybridBitSet` have gradually disappeared (e.g. #116152) and there are now few enough that they can be replaced with `BitSet` or `ChunkedBitSet`, and `HybridBitSet` can be removed, cutting more than 700 lines of code.

r? `@Mark-Simulacrum`
2024-11-29 09:03:50 +00:00
Nicholas Nethercote
4846c1922d Remove HybridBitSet.
It's no longer used.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
b7ff2aedd9 Stop using HybridBitSet in SparseBitMatrix.
Use `ChunkedBitSet` instead.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
0df6a018e1 Stop using HybridBitSet in dataflow diffs.
As part of the larger goal of reducing `HybridBitSet` use in general.
This code is for debugging only and isn't performance sensitive, so
`ChunkedBitSet` should be fine.
2024-11-29 17:23:34 +11:00
Nicholas Nethercote
346929cb80 Remove unused HybridBitSet methods from BitSetExt. 2024-11-29 17:23:34 +11:00
Nicholas Nethercote
ded4dfde19 Speed up ChunkedBitIter
The current implementation is slow because it does an operation for
every bit in the set, even zero bits. So if you have a large bitset with
many zero bits (which is common) it's very slow.

This commit improves the iterator to skip over `Zeros` chunks in a
single step, and uses the fast `BitIter` for `Mixed` chunks. It also
removes the existing `fold` implementation, which was only there because
the old iterator was slow.
2024-11-29 17:23:32 +11:00
Nicholas Nethercote
ff78002566 Tiny ChunkedBitSet improvements.
- Fix a typo in a comment.
- Remove unnecessary `Chunk::` qualifiers.
- Rename `ChunkedBitIter::bitset` as `ChunkedBitIter::bit_set`, because
  `bit_set` is the form used everywhere else.
- Avoid some unnecessary local variables.
2024-11-29 17:01:48 +11:00
Nicholas Nethercote
15b24c46b4 Clarify ChunkSize invariants.
`ChunkedBitSet::is_empty` currently does an unnecessary check. This
commit removes that check and adds clarifying comments and an assertion
that demonstrate why it's unnecessary.
2024-11-29 17:01:48 +11:00
bors
cb2bd2bb06 Auto merge of #133608 - Zalathar:spans-revert, r=jieyouxu
Revert #133418 (Store coverage source regions as `Span`) due to regression #133606

This reverts commit adf9b5fcd1, reversing changes made to af1ca153d4.

Reverting #133418 due to regressions reported at #133606.

r? jieyouxu
2024-11-29 05:38:09 +00:00
Zalathar
9461f4296f Revert "Rollup merge of #133418 - Zalathar:spans, r=jieyouxu"
This reverts commit adf9b5fcd1, reversing
changes made to af1ca153d4.

Reverting due to <https://github.com/rust-lang/rust/issues/133606>.
2024-11-29 14:57:01 +11:00
Maybe Waffle
cfb78419cd implement checks for tail calls
this implements checks necessary to guarantee that we can actually
perform a tail call. while extremely restrictive, this is what is
documented in the RFC, and all these checks are needed for one reason or
another.
2024-11-29 04:44:41 +01:00
bors
d6f88291f3 Auto merge of #133409 - RalfJung:target-consistency, r=lcnr
ensure JSON-defined targets are consistent

We have a `check_consistency` check that ensures some invariants which (presumably) the rest of the compiler relies on. However, JSON targets can easily be written in a way that violates those invariants. So this PR applies the same consistency check to JSON targets that we already enforce for built-in targets.

I have converted many of the assertions in that function to new macros that show a nice error instead of a panic; if people are okay with the general approach here, I can do that for the rest of the checks as well.
2024-11-29 01:35:20 +00:00
Orion Gonzalez
1e4817cd33 bless the tests and add a new one 2024-11-29 00:45:14 +01:00
Orion Gonzalez
b36dcc1a38 Improve the diagnostic of fn item in variadic fn 2024-11-29 00:45:14 +01:00
bors
d53f0b1d8e Auto merge of #123244 - Mark-Simulacrum:share-inline-never-generics, r=saethlin
Enable -Zshare-generics for inline(never) functions

This avoids inlining cross-crate generic items when possible that are
already marked inline(never), implying that the author is not intending
for the function to be inlined by callers. As such, having a local copy
may make it easier for LLVM to optimize but mostly just adds to binary
bloat and codegen time. In practice our benchmarks indicate this is
indeed a win for larger compilations, where the extra cost in dynamic
linking to these symbols is diminished compared to the advantages in
fewer copies that need optimizing in each binary.

It might also make sense it expand this with other heuristics (e.g.,
`#[cold]`) in the future, but this seems like a good starting point.

FWIW, I expect that doing cleanup in where we make the decision
what should/shouldn't be shared is also a good idea. Way too
much code needed to be tweaked to check this. But I'm hoping
to leave that for a follow-up PR rather than blocking this on it.
2024-11-28 21:44:34 +00:00
Scott Mabin
727f6a6d13 Add +forced-atomics feature to esp32s2 2024-11-28 21:41:34 +00:00
Maybe Lapkin
8e77349782 fix a comment with uneven number of backticks in rustc_mir_build
this is funny though! apparently tidy parsed `.gitignore`, but did not
recognize unignore lines (`!...`), so tidy was ignoring `rustc_mir_build`
this whole time (at least for some lints?).
2024-11-28 21:54:27 +01:00
Michael Goulet
0ac93cd579 Structurally resolve before adjust_for_branches 2024-11-28 20:40:27 +00:00
Nicholas Nethercote
accdfa1e52 Update -Zshow-span help message.
To clarify how it works.
2024-11-29 06:10:16 +11:00
Nicholas Nethercote
76adf05cfb Rename -Zparse-only.
I was surprised to find that running with `-Zparse-only` only parses the
crate root file. Other files aren't parsed because that happens later
during expansion.

This commit renames the option and updates the help message to make this
clearer.
2024-11-29 06:10:15 +11:00
Mark Rousskov
4a216a25d1 Share inline(never) generics across crates
This reduces code sizes and better respects programmer intent when
marking inline(never). Previously such a marking was essentially ignored
for generic functions, as we'd still inline them in remote crates.
2024-11-28 13:43:05 -05:00
Taiki Endo
df8feb5067 Support floats in input/output in vector registers of PowerPC inline assembly 2024-11-29 03:10:07 +09:00
Taiki Endo
0c8e36bb30 Fix target_feature handling in freg of LoongArch inline assembly 2024-11-29 03:01:33 +09:00
Esteban Küber
8574f374e2 Do not call extern_crate on current trait on crate mismatch errors
When we encounter an error caused by traits/types of different versions of the same crate, filter out the current crate when collecting spans to add to the context so we don't call `extern_crate` on the `DefId` of the current crate, which is meaningless and ICEs.

Produced output with this filter:

```
error[E0277]: the trait bound `foo::Struct: Trait` is not satisfied
  --> y.rs:13:19
   |
13 |     check_trait::<foo::Struct>();
   |                   ^^^^^^^^^^^ the trait `Trait` is not implemented for `foo::Struct`
   |
note: there are multiple different versions of crate `foo` in the dependency graph
  --> y.rs:7:1
   |
4  | extern crate foo;
   | ----------------- one version of crate `foo` is used here, as a direct dependency of the current crate
5  |
6  | pub struct Struct;
   | ----------------- this type implements the required trait
7  | pub trait Trait {}
   | ^^^^^^^^^^^^^^^ this is the required trait
   |
  ::: x.rs:4:1
   |
4  | pub struct Struct;
   | ----------------- this type doesn't implement the required trait
5  | pub trait Trait {}
   | --------------- this is the found trait
   = note: two types coming from two different versions of the same crate are different types even if they look the same
   = help: you can use `cargo tree` to explore your dependency tree
note: required by a bound in `check_trait`
  --> y.rs:10:19
   |
10 | fn check_trait<T: Trait>() {}
   |                   ^^^^^ required by this bound in `check_trait`
```

Fix #133563.
2024-11-28 17:55:52 +00:00
bors
7e565cce6a Auto merge of #133468 - lcnr:uwu4, r=BoxyUwU
always create `DefId`s for anon consts

but don't use them anywhere, we intentionally don't encode them in the crate metadata.

best reviewed by disabling whitespace.

This pretty much reimplements #133285 while adding the tests of #133455. Fixes #133064

r? `@BoxyUwU` `@compiler-errors`
2024-11-28 15:58:17 +00:00
clubby789
71b698c0b8 Replace Symbol::intern calls with preinterned symbols 2024-11-28 15:45:27 +00:00
clubby789
72d2db7bf4 Implement lint against Symbol::intern on a string literal 2024-11-28 15:45:25 +00:00
Taiki Endo
0f8ebba54a Support #[repr(simd)] types in input/output of PowerPC inline assembly 2024-11-29 00:24:36 +09:00
Julian Frimmel
67d2f3f685 Reword error message of reserved AVR registers
Those are reserved as per the GCC (and thus LLVM) ABI, which is distinct from an
issue. The rewording was requested in this [review].

[review]: https://github.com/rust-lang/rust/pull/131323#issuecomment-2479178721
2024-11-28 16:12:04 +01:00
Julian Frimmel
ba73166556 Support clobber_abi for AVR inline assembly
This commit adds the relevant registers to the list of clobbered regis-
ters (part of #93335). This follows the [ABI documentation] of AVR-GCC:

> The [...] call-clobbered general purpose registers (GPRs) are
> registers that might be destroyed (clobbered) by a function call.
>
> - **R18–R27, R30, R31**
>
>   These GPRs are call clobbered. An ordinary function may use them
>   without restoring the contents. [...]
>
> - **R0, T-Flag**
>
>   The temporary register and the T-flag in SREG are also call-
>   clobbered, but this knowledge is not exposed explicitly to the
>   compiler (R0 is a fixed register).

Therefore this commit lists the aforementioned registers `r18–r27`,
`r30` and `r31` as clobbered registers. Since the `r0` register (listed
above as well) is not available in inline assembly at all (potentially
because the AVR-GCC considers it a fixed register causing the register
to never be used in register allocation and LLVM adopting this), there
is no need to list it in the clobber list (the `r0`-variant is not even
available). A comment was added to ensure, that the `r0` gets added to
the clobber-list once the register gets usable in inline ASM.
Since the SREG is normally considered clobbered anyways (unless the user
supplies the `preserve_flags`-option), there is no need to explicitly
list a bit in this register (which is not possible to list anyways).

Note, that this commit completely ignores the case of interrupts (that
are described in the ABI-specification), since every register touched in
an ISR need to be saved anyways.

[ABI documentation]: https://gcc.gnu.org/wiki/avr-gcc#Call-Used_Registers
2024-11-28 16:12:02 +01:00
Mads Marquart
9b6dfdd2ab Mark visionOS as supporting std
Cargo's -Zbuild-std has recently started checking this field, which
causes it to fail to compile even though we have full support for the
standard library on these targets.
2024-11-28 13:53:38 +01:00