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2 Commits

Author SHA1 Message Date
Tsukasa OI
5ebdec5ac2 rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list 
Despite that the `fflags` register (representing floating point
exception flags) is stated as a flag register in the reference, it's not
in the default clobber list of the RISC-V inline assembly and it would
be better to fix it.
 2025-09-15 02:16:34 +00:00
Guillaume Gomez
a27f3e3fd1 Rename tests/codegen into tests/codegen-llvm 2025-07-22 14:28:48 +02:00