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2629 Commits

Author SHA1 Message Date
bjorn3
98122a49ce Make the _mm_movemask_epi8 test a non palindrome 2019-08-02 16:31:38 +02:00
bjorn3
7bdc18925d Remove simd_rem intrinsic definition 
It is unused
 2019-08-02 16:31:24 +02:00
gnzlbg
713a7f11e1 Update i586-unknown-linux-gnu codegen with LLVM9 bugfixes 2019-08-02 11:45:12 +02:00
gnzlbg
57ba80a914 Disable Game Boy Advance build job temporarily 2019-08-02 11:45:12 +02:00
gnzlbg
174fd52167 formatting 2019-08-02 11:45:12 +02:00
gnzlbg
eb8ddf2fd3 Update LLVM9 code generation on Windows 2019-08-02 11:45:12 +02:00
gnzlbg
95cacb4cb9 Update codegen of _mm256_set1_epi64x for x86 32-bit 2019-08-02 11:45:12 +02:00
gnzlbg
58bff6d32e White-list new codegen for _mm_broadcastq_epi64 
Opened #791 .
 2019-08-02 11:45:12 +02:00
gnzlbg
44ffb1860f LLVM9 started emitting more single precision floating-point intrinsics for double-precision operations 2019-08-02 11:45:12 +02:00
gnzlbg
9969a01d60 Migrate Azure to the rust-lang2 org 2019-08-02 11:45:12 +02:00
Nathan Wiebe Neufeldt
da1241df4a Fix doc punctuation in core_arch/src/mips/msa.rs 2019-07-25 00:50:43 +02:00
Nathan Wiebe Neufeldt
ced45f6eb3 Even more doc formatting core_arch/src/mips/msa.rs 2019-07-25 00:50:43 +02:00
Nathan Wiebe Neufeldt
7ac384096b More doc formatting in core_arch/src/mips/msa.rs 2019-07-25 00:50:43 +02:00
Nathan Wiebe Neufeldt
0010f5bb4b Fix typos in core_arch documentation 2019-07-25 00:50:43 +02:00
Jonas Schievink
03f389ff6d Adjust #[doc(include)] paths for rustdoc change 2019-07-23 17:14:01 +02:00
bjorn3
a035568e7d Remove unnecessary \n from cpuid 2019-07-23 16:47:27 +02:00
gnzlbg
e4d54a44bf Revert PR 769 2019-07-15 16:28:24 +02:00
Johannes Maibaum
2f2f78ada1 Add ARM Neon vmnv_p8/vmvnq_p8 bw not intrinsics 2019-07-15 09:22:17 +02:00
Johannes Maibaum
c55edc23b4 Add ARM Neon vmvn_*/vmvnq_* bitwise not intrinsics 2019-07-15 09:22:17 +02:00
gnzlbg
ec7697de1b Disable mips MSA builds - I dont think they can ever work except for the r6 targets 2019-07-14 15:29:19 +02:00
gnzlbg
0357faa7c0 Try harder to parse invalid UTF8 on Windows 2019-07-14 15:29:19 +02:00
gnzlbg
800039bd23 Update with libc system 2019-07-14 15:29:19 +02:00
gnzlbg
8059e580e3 Upload documentation to gh-pages 2019-07-14 15:29:19 +02:00
gnzlbg
f61cb90d87 Try windows 2019-07-14 15:29:19 +02:00
gnzlbg
dffdd66d81 Disable wasm32 simd128 tests 2019-07-14 15:29:19 +02:00
gnzlbg
d88e30a204 Add windows jobs 2019-07-14 15:29:19 +02:00
gnzlbg
f7a91c7a57 Add Azure Pipelines 2019-07-14 15:29:19 +02:00
Luca Barbato
b39c3262f1 Rustfmt altivec.rs 2019-07-11 14:39:54 +02:00
Luca Barbato
eae484cc2b Demote powerpc64 tests until qemu is fixed 
Big Endian powerpc64 is not really supported anymore by IBM.
 2019-07-11 14:39:54 +02:00
Luca Barbato
89cb7025cb Add imm5 and imm_s5 to the common macros 2019-07-11 14:39:54 +02:00
Luca Barbato
eef9e33e6a Add Altivec vec_ld 2019-07-11 14:39:54 +02:00
Luca Barbato
6f9061f78b Add Altivec vec_floor 2019-07-11 14:39:54 +02:00
Luca Barbato
1f96c3192e Add a fuzzy comparison test for f32 2019-07-11 14:39:54 +02:00
Luca Barbato
cce9d50f9b Add Altivec vec_abs for f32 2019-07-11 14:39:54 +02:00
Luca Barbato
2339c48706 Add Altivec vec_expte 2019-07-11 14:39:54 +02:00
Luca Barbato
3525b9d7a3 Add Altivec vec_sub for f32 as well 2019-07-11 14:39:54 +02:00
Luca Barbato
2c1e3fdb37 Add single argument test macro 2019-07-11 14:39:54 +02:00
Luca Barbato
0b3ff21135 Add Altivec vec_cmple and vec_cmplt 2019-07-11 14:39:54 +02:00
gnzlbg
8cec101751 Allow unused items in verification tests 2019-07-09 01:37:07 +02:00
gnzlbg
1253c1daed Enable warnings globally 2019-07-09 01:37:07 +02:00
gnzlbg
686b813f5d Update repo name 2019-07-09 01:37:07 +02:00
gnzlbg
127f13f10f Fix assert_instr tests 2019-07-08 22:58:19 +02:00
Yuki Okushi
e3ed80dd67 Fix typo 2019-07-08 22:54:13 +02:00
gnzlbg
832259621c Fix data-race in assert_instr 2019-07-08 13:15:07 +02:00
gnzlbg
657f778871 Fix libcore build 2019-07-08 13:15:07 +02:00
Yuki Okushi
6163c1d6ff Fix typo 2019-07-07 09:17:15 +02:00
dependabot-preview[bot]
deb328f6c6 Update rand requirement from 0.6 to 0.7 
Updates the requirements on [rand](https://github.com/rust-random/rand) to permit the latest version.
- [Release notes](https://github.com/rust-random/rand/releases)
- [Changelog](https://github.com/rust-random/rand/blob/master/CHANGELOG.md)
- [Commits](https://github.com/rust-random/rand/commits)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-01 11:59:44 +02:00
Jonas Schievink
a0fb95df37 Adjust #[doc(include)] paths for rustdoc change 2019-06-23 20:15:34 +02:00
Sergey Pepyakin
1176e480a0 Stabilize unreachable. 2019-06-04 09:09:03 +02:00
hygonsoc
6369621e79 add Hygon Dhyana CPU Vendor ID("HygonGenuine") checking 
As Hygon Dhyana originates from AMD technology and shares most of the architecture with
AMD's family 17h, but with different CPU Vendor ID("HygonGenuine")/Family series number(Family 18h).

for CPUID feature bits, Hygon Dhyana(family 18h) share the same definition with AMD family 17h.
AMD CPUID specification is https://www.amd.com/system/files/TechDocs/25481.pdf.

Related Hygon kernel patch can be found on
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
 2019-05-25 15:51:21 +02:00