This involves moving from the ACLE intrinsic definitions (which aren't
available for SVE at this point) to a JSON file. This was derived from
ARM's documentation[^1], and then relicensed under `MIT OR Apache-2.0` for
use in this repository.
[^1]: https://developer.arm.com/architectures/instruction-sets/intrinsics
These intrinsics actually are zeroing, so we should be upfront
that these still return a valid value in reality. At most,
we might in the future want to use a "freezing" semantics here.
In any case, they are definitely not returning MaybeUninit,
or any other possibly-poison value.
This is a follow-up to #1345 where these appeared as unstable in the
standard library docs because they are only stabilized for ARM. They
were missed in the original PR.
- Fix a typo in the feature name
- Update docs to reflect changes in behavior on invalid ordering in
stabilized PR: invalid ordering is no longer UB, just causes panic as
well as compare_exchange
This commit adds intrinsics to the `wasm32` to support the [relaxed SIMD
proposal][proposal]. These are added with the same naming conventions of
existing simd-related intrinsics for wasm which is similar to the
instruction name but matches sign in a few places.
This additionally updates Wasmtime to execute tests with support for the
relaxed simd proposal. No release has been made yet so this uses the
`dev` release, and I can make a PR in April when the support in Wasmtime
has been released to an official release. The `wasmprinter` crate is
also updated to understand these instruction opcodes as well.
Documentation has been added for all intrinsics, but tests have only
been added for some of them so far. I hope to follow-up later with more
tests.
[proposal]: https://github.com/WebAssembly/relaxed-simd
