7 Commits

Author SHA1 Message Date
Paul Murphy
4945d21ed9 Implement ppc/ppc64 preserves_flags option for inline asm
Implemented preserves_flags on powerpc by making it do
nothing. This prevents having two different ways to mark
`cr0` as clobbered. clang and gcc alias `cr0` to `cc`.

The gcc inline documentation does not state what this does
on powerpc* targets, but inspection of the source shows
it is equivalent to condition register field `cr0`, so it
should not be added.
2025-10-14 10:05:07 -05:00
Paul Murphy
3c09d4a582 Allow vector-scalar (vs) registers in ppc inline assembly
Where supported, VSX is a 64x128b register set which encompasses
both the floating point and vector registers.

In the type tests, xvsqrtdp is used as it is the only two-argument
vsx opcode supported by all targets on llvm. If you need to copy
a vsx register, the preferred way is "xxlor xt, xa, xa".
2025-10-14 09:52:56 -05:00
Stuart Cook
46be365a60 Rollup merge of #146831 - taiki-e:powerpc-clobber, r=Amanieu
Support ctr and lr as clobber-only registers in PowerPC inline assembly

Follow-up to rust-lang/rust#131341.

CTR and LR are marked as volatile in all ABIs, but I skipped them in rust-lang/rust#131341 due to they are currently marked as reserved.
dd7fda5700/compiler/rustc_target/src/asm/powerpc.rs (L209-L212)

However, they are actually only unusable as input/output of inline assembly, and should be fine to support as clobber-only registers as discussed in [#t-compiler > ppc/ppc64 inline asm support](https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/ppc.2Fppc64.20inline.20asm.20support/with/540413845).

r? ````@Amanieu```` or ````@workingjubilee````

cc ````@programmerjake````

````@rustbot```` label +O-PowerPC +A-inline-assembly
2025-09-22 20:25:14 +10:00
Folkert de Vries
3565b0699d emit attribute for readonly non-pure inline assembly 2025-09-21 21:16:06 +02:00
Taiki Endo
f4b876867d Support ctr and lr as clobber-only registers in PowerPC inline assembly 2025-09-21 13:48:22 +09:00
Tsukasa OI
5ebdec5ac2 rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list
Despite that the `fflags` register (representing floating point
exception flags) is stated as a flag register in the reference, it's not
in the default clobber list of the RISC-V inline assembly and it would
be better to fix it.
2025-09-15 02:16:34 +00:00
Guillaume Gomez
a27f3e3fd1 Rename tests/codegen into tests/codegen-llvm 2025-07-22 14:28:48 +02:00