1434 Commits

Author SHA1 Message Date
Alisa Sireneva
420544a34a Move wasm throw intrinsic back to unwind
rustc assumes that regular `extern "Rust"` functions unwind only if the
`unwind` panic runtime is linked. `throw` was annotated as such, but
unwound unconditionally. This could cause UB when a crate built with `-C
panic=abort` called `throw` from `core` built with `-C panic=unwind`,
since no terminator was added to handle the panic arising from calling an
allegedly non-unwinding `extern "Rust"` function.

rustc was taught to recognize this condition since
https://github.com/rust-lang/rust/pull/144225 and prevented such
linkage, but this caused regressions in
https://github.com/rust-lang/rust/issues/148246, since this meant that
Emscripten projects could not be built with `-C panic=abort` without
recompiling std.

The most straightforward solution would be to move `throw` into the
`panic_unwind` crate, so that it's only compiled if the panic runtime is
guaranteed to be `unwind`, but this is messy due to our architecture.
Instead, move it into `unwind::wasm`, which is only compiled for
bare-metal targets that default to `panic = "abort"`, rendering the
issue moot.
2025-10-30 15:13:32 +03:00
bors
ce4beebecb Auto merge of #146683 - clarfonthey:safe-intrinsics, r=RalfJung,Amanieu
Mark float intrinsics with no preconditions as safe

Note: for ease of reviewing, the list of safe intrinsics is sorted in the first commit, and then safe intrinsics are added in the second commit.

All *recently added* float intrinsics have been correctly marked as safe to call due to the fact that they have no preconditions. This adds the remaining float intrinsics which are safe to call to the safe intrinsic list, and removes the unsafe blocks around their calls.

---

Side note: this may want a try run before being added to the queue, since I'm not sure if there's any tier-2 code that uses these intrinsics that might not be tested on the usual PR flow. We've already uncovered a few places in subtrees that do this, and it's worth double-checking before clogging up the queue.
2025-09-22 14:35:46 +00:00
ltdk
055e05a338 Mark float intrinsics with no preconditions as safe 2025-09-21 20:37:51 -04:00
Sayantan Chakraborty
c1242fab74 Merge pull request #1921 from a4lg/riscv-inline-asm-general-improvements
RISC-V: Improvements of inline assembly uses
2025-09-15 18:39:49 +00:00
Folkert de Vries
5dd0fdcd67 Merge pull request #1919 from sayantn/fix-vreinterpret
Remove big-endian swizzles from `vreinterpret`
2025-09-15 08:18:20 +00:00
Tsukasa OI
8df078a3f0 RISC-V: Improvements of inline assembly uses
This commit performs various improvements (better register allocation,
less register clobbering on the worst case and better readability) of
RISC-V inline assembly use cases.

Note that it does not change the `p` module (which defines the "P"
extension draft instructions but very likely to change).

1.  Use `lateout` as possible.
    Unlike `out(reg)` and `in(reg)` pair, `lateout(reg)` and `in(reg)`
    can share the same register because they state that the late-output
    register is written after all the reads are performed.
    It can improve register allocation.
2.  Add `preserves_flags` option as possible.
    While RISC-V doesn't have _regular_ condition codes, RISC-V inline
    assembly in the Rust language assumes that some registers
    (mainly vector state registers) may be overwritten by default.
    By adding `preserves_flags` to the intrinsics corresponding
    instructions without overwriting them, it can minimize register
    clobbering on the worst case.
3.  Use trailing semicolon.
    As `asm!` declares an action and it doesn't return a value by
    itself, it would be better to have trailing semicolon to denote that
    an `asm!` call is effectively a statement.
4.  Make most of `asm!` calls multi-lined.
    `rustfmt` makes some simple (yet long) `asm!` calls multi-lined but
    it does not perform formatting of complex `asm!` calls with inputs
    and/or outputs.  To keep consistency, it makes most of the `asm!`
    calls multi-lined.
2025-09-14 05:08:19 +00:00
Sayantan Chakraborty
269cecc91c Merge pull request #1918 from a4lg/riscv-aes64im-lower-requirements
RISC-V: "Lower" requirements of `aes64im`
2025-09-11 19:59:18 +00:00
sayantn
bb31725e67 Remove big-endian swizzles from vreinterpret 2025-09-12 01:20:34 +05:30
Tsukasa OI
e54cc43867 RISC-V: "Lower" requirements of aes64im
This instruction is incorrectly categorized as the same one as
`aes64ks1i` and `aes64ks2` (that should require `zkne || zknd` but
currently require `zkne && zknd`) but `aes64im` only requires
the Zknd extension.

This commit fixes the category of this intrinsic (lowering the
requirements from the Rust perspective but it does not actually lower
it from the RISC-V perspective).
2025-09-11 06:42:10 +00:00
WANG Rui
614dab3ed2 loongarch: Align intrinsic signatures with LLVM 2025-09-10 23:10:19 +08:00
Folkert de Vries
93101b5783 s390x: use the new u128::funnel_shl 2025-09-06 14:32:36 +02:00
Folkert de Vries
e1a3b8bdc1 Merge pull request #1911 from nikic/remove-hack
Remove some llvm workarounds
2025-09-03 13:16:03 +00:00
Tsukasa OI
4679533732 RISC-V: Lower requirements of clmul and clmulh
They don't need full "Zbc" extension but only its subset: the "Zbkc"
extension.  Since the compiler implies `zbkc` from `zbc`, it's safe to
use `#[target_feature(enable = "zbkc")]`.
2025-09-03 02:13:35 +00:00
Nikita Popov
18fa6d917c Remove some llvm workarounds 2025-09-02 10:48:42 +02:00
Folkert de Vries
ae648be783 use llvm.roundeven on arm 2025-08-29 12:15:41 +02:00
Amanieu d'Antras
b2189b8ff6 Merge pull request #1903 from folkertdev/s390x-llvm-21-fixes
`s390x` llvm 21 improvements
2025-08-21 20:31:06 +00:00
Folkert de Vries
98bd1d7445 use simd_saturating_{add, sub} on neon 2025-08-21 10:25:00 +02:00
Amanieu d'Antras
0b0c42478f Merge pull request #1901 from folkertdev/wasm-read-unaligned
wasm: use `{read, write}_unaligned` methods
2025-08-20 20:44:05 +00:00
Folkert de Vries
6d74280ae4 Merge pull request #1899 from dpaoliello/arm64ec
Add testing for Arm64EC Windows
2025-08-20 20:42:51 +00:00
Folkert de Vries
45af206618 s390x: link to a missed optimization 2025-08-20 22:20:30 +02:00
Folkert de Vries
e9162f221a s390x: implement vec_sld using fshl 2025-08-20 22:20:30 +02:00
Folkert de Vries
dfa95c6fa4 s390x: implement vec_subc_u128 using overflowing_sub 2025-08-20 22:20:29 +02:00
Folkert de Vries
e1a1b1ded2 s390x: implement vec_mulo using core::intrinsics::simd 2025-08-20 22:20:28 +02:00
Folkert de Vries
d5cb1c49fa wasm: use {read, write}_unaligned methods 2025-08-20 22:11:32 +02:00
Folkert de Vries
1cda88aca1 s390x: implement vec_mule using core::intrinsics::simd 2025-08-20 22:11:16 +02:00
Folkert de Vries
97d64665b9 s390x: add assert_instr for vec_extend 2025-08-20 22:11:16 +02:00
Folkert de Vries
c5ec0960f0 s390x: add assert_instr for vec_round 2025-08-20 22:11:16 +02:00
Folkert de Vries
fa163a1fca s390x: define unpack_low using core::intrinsics::simd 2025-08-20 22:11:15 +02:00
Nikita Popov
3302e3e09a Adjust immediate for vrndscalepd tests
The immediate here encodes both the rounding mode (in the low bits)
and the scale (in the high bits). Make sure the scale is non-zero.
2025-08-20 11:23:46 +02:00
Nikita Popov
92f6310890 Work around selection failure without avx512vl 2025-08-20 11:23:46 +02:00
Nikita Popov
4a8b8231b1 Add missing avx512vl target features 2025-08-20 11:23:46 +02:00
Nikita Popov
135de7c8df Use intrinsics for some s390x operations 2025-08-20 11:23:30 +02:00
Nikita Popov
f9bc63d78f Drop no longer needed feature gates 2025-08-20 11:23:30 +02:00
sayantn
100d19ce5b Stabilize sse4a and tbm target features
- remove some stabilized target features from `gate.rs`
2025-08-14 02:07:40 +05:30
Daniel Paoliello
f2c0c3dd44 Add testing for Arm64EC Windows 2025-08-10 13:19:06 -07:00
The rustc-josh-sync Cronjob Bot
49aa0ecc7b Merge ref '32e7a4b92b10' from rust-lang/rust
Pull recent changes from https://github.com/rust-lang/rust via Josh.

Upstream ref: 32e7a4b92b
Filtered ref: 56d8aa13f54944edb711f3bdd7013b082dbaa65b

This merge was created using https://github.com/rust-lang/josh-sync.
2025-07-31 04:20:38 +00:00
Alisa Sireneva
17519aeaef Allow ffi_unwind_calls for arch::wasm32::throw 2025-07-25 18:28:03 +03:00
Folkert de Vries
cc15f022e7 Merge pull request #1879 from heiher/loong-simd-unified-types
loongarch: Use unified data types for SIMD intrinsics
2025-07-25 13:46:59 +00:00
WANG Rui
49ea48d952 loongarch: Use unified data types for SIMD intrinsics 2025-07-25 09:31:58 +08:00
Aurelia Molzer
be947d4d2b Add non-temporal note for maskmoveu_si128
Like any other non-temporal instructions this has additional safety requirements
due to the mismatch with the Rust memory model. It is vital to know when using
this instruction.
2025-07-24 14:52:26 +02:00
Folkert de Vries
b658b3d251 work around not being able to project out of SIMD values any more 2025-07-22 19:32:09 +02:00
Amanieu d'Antras
8fe55684d8 Merge pull request #1860 from folkertdev/stdarch-test-cleanup
`stdarch-test`: various cleanups
2025-07-18 20:27:56 +00:00
WANG Rui
da892b54be loongarch: Mark SIMD intrinsics without memory access as safe 2025-07-18 20:42:19 +08:00
WANG Rui
b57ff35641 loongarch: Mark partial basic intrinsics as safe 2025-07-18 11:52:17 +08:00
Folkert de Vries
b74c4825cb test for the high version of a number of instructions 2025-07-17 02:12:15 +02:00
Folkert de Vries
bdd1ca1eea aarch64: check for trn1 and trn2 2025-07-15 22:17:03 +02:00
Folkert de Vries
c13e3aa6b4 aarch64: check for uzp1 and uzp2 2025-07-15 22:17:02 +02:00
Folkert de Vries
ce3eabfd70 aarch64: check for zip1 and zip2 2025-07-15 22:17:02 +02:00
Folkert de Vries
f6f6715990 s390x: fix tests that matched on prefix of instruction 2025-07-15 20:20:46 +02:00
Amanieu d'Antras
2aaa584094 Merge pull request #1872 from folkertdev/aarch64-horizontal-add
`aarch64`: use `intrinsics::simd` for horizontal add and `abs`
2025-07-15 00:19:05 +00:00