some clippy fixes
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committed by
Amanieu d'Antras
parent
1bc289da3a
commit
fddd05bd7f
@@ -7925,7 +7925,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 {
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#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
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pub fn vcvth_n_f16_s16<const N: i32>(a: i16) -> f16 {
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static_assert!(N >= 1 && N <= 16);
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vcvth_n_f16_s32::<N>(a as i32) as f16
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vcvth_n_f16_s32::<N>(a as i32)
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}
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#[doc = "Fixed-point convert to floating-point"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"]
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@@ -7972,7 +7972,7 @@ pub fn vcvth_n_f16_s64<const N: i32>(a: i64) -> f16 {
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#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
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pub fn vcvth_n_f16_u16<const N: i32>(a: u16) -> f16 {
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static_assert!(N >= 1 && N <= 16);
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vcvth_n_f16_u32::<N>(a as u32) as f16
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vcvth_n_f16_u32::<N>(a as u32)
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}
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#[doc = "Fixed-point convert to floating-point"]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"]
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@@ -24082,7 +24082,6 @@ pub fn vrsqrtes_f32(a: f32) -> f32 {
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#[doc = "Reciprocal square-root estimate."]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"]
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#[inline]
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#[target_feature(enable = "neon,fp16")]
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#[cfg_attr(test, assert_instr(frsqrte))]
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#[target_feature(enable = "neon,fp16")]
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#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
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@@ -20,10 +20,10 @@
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//! Section 10.1 of ACLE says:
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//!
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//! - "In the sequence of Arm architectures { v5, v5TE, v6, v6T2, v7 } each architecture includes
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//! its predecessor instruction set."
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//! its predecessor's instruction set."
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//!
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//! - "In the sequence of Thumb-only architectures { v6-M, v7-M, v7E-M } each architecture includes
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//! its predecessor instruction set."
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//! its predecessor's instruction set."
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//!
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//! From that info and from looking at how LLVM features work (using custom targets) we can identify
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//! features that are subsets of others:
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@@ -38,7 +38,7 @@
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//! *NOTE*: Section 5.4.7 of ACLE says:
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//!
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//! - "__ARM_FEATURE_DSP is defined to 1 if the DSP (v5E) instructions are supported and the
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//! intrinsics defined in Saturating intrinsics are available."
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//! intrinsics defined in Saturating intrinsics are available."
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//!
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//! This does *not* match how LLVM uses the '+dsp' feature; this feature is not set for v5te
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//! targets so we have to work around this difference.
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@@ -777,8 +777,8 @@ pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t);
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
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pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t);
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/// Arm-specific type containing four `float16x8_t` vectors.
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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