convert _mm_maskz_srli_epi16 to const generics
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Amanieu d'Antras
parent
e6d9f003b4
commit
dabaca41ca
@@ -5424,15 +5424,11 @@ pub unsafe fn _mm_mask_srli_epi16<const IMM8: i32>(
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_srli_epi16&expand=5506)
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#[inline]
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#[target_feature(enable = "avx512bw,avx512vl")]
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#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))]
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#[rustc_args_required_const(2)]
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pub unsafe fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i, imm8: i32) -> __m128i {
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macro_rules! call {
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($imm8:expr) => {
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_mm_srli_epi16::<$imm8>(a)
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};
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}
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let shf = constify_imm8_sae!(imm8, call);
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#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
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#[rustc_legacy_const_generics(2)]
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pub unsafe fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
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static_assert_imm8!(IMM8);
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let shf = _mm_srli_epi16::<IMM8>(a);
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let zero = _mm_setzero_si128().as_i16x8();
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transmute(simd_select_bitmask(k, shf.as_i16x8(), zero))
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}
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@@ -14750,9 +14746,9 @@ mod tests {
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#[simd_test(enable = "avx512bw,avx512vl")]
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unsafe fn test_mm_maskz_srli_epi16() {
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let a = _mm_set1_epi16(1 << 1);
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let r = _mm_maskz_srli_epi16(0, a, 2);
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let r = _mm_maskz_srli_epi16::<2>(0, a);
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assert_eq_m128i(r, _mm_setzero_si128());
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let r = _mm_maskz_srli_epi16(0b11111111, a, 2);
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let r = _mm_maskz_srli_epi16::<2>(0b11111111, a);
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let e = _mm_set1_epi16(0);
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assert_eq_m128i(r, e);
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}
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