convert _mm_maskz_srli_epi16 to const generics

This commit is contained in:
Rémy Rakic
2021-03-05 00:30:12 +01:00
committed by Amanieu d'Antras
parent e6d9f003b4
commit dabaca41ca

View File

@@ -5424,15 +5424,11 @@ pub unsafe fn _mm_mask_srli_epi16<const IMM8: i32>(
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_srli_epi16&expand=5506) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_srli_epi16&expand=5506)
#[inline] #[inline]
#[target_feature(enable = "avx512bw,avx512vl")] #[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
#[rustc_args_required_const(2)] #[rustc_legacy_const_generics(2)]
pub unsafe fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i, imm8: i32) -> __m128i { pub unsafe fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
macro_rules! call { static_assert_imm8!(IMM8);
($imm8:expr) => { let shf = _mm_srli_epi16::<IMM8>(a);
_mm_srli_epi16::<$imm8>(a)
};
}
let shf = constify_imm8_sae!(imm8, call);
let zero = _mm_setzero_si128().as_i16x8(); let zero = _mm_setzero_si128().as_i16x8();
transmute(simd_select_bitmask(k, shf.as_i16x8(), zero)) transmute(simd_select_bitmask(k, shf.as_i16x8(), zero))
} }
@@ -14750,9 +14746,9 @@ mod tests {
#[simd_test(enable = "avx512bw,avx512vl")] #[simd_test(enable = "avx512bw,avx512vl")]
unsafe fn test_mm_maskz_srli_epi16() { unsafe fn test_mm_maskz_srli_epi16() {
let a = _mm_set1_epi16(1 << 1); let a = _mm_set1_epi16(1 << 1);
let r = _mm_maskz_srli_epi16(0, a, 2); let r = _mm_maskz_srli_epi16::<2>(0, a);
assert_eq_m128i(r, _mm_setzero_si128()); assert_eq_m128i(r, _mm_setzero_si128());
let r = _mm_maskz_srli_epi16(0b11111111, a, 2); let r = _mm_maskz_srli_epi16::<2>(0b11111111, a);
let e = _mm_set1_epi16(0); let e = _mm_set1_epi16(0);
assert_eq_m128i(r, e); assert_eq_m128i(r, e);
} }