std_detect: Linux 6.16 support for RISC-V

It adds feature detection of 1 extension (new in std_detect).

New RISC-V Extension:

1.  "Zabha"
This commit is contained in:
Tsukasa OI
2025-07-31 07:39:10 +00:00
parent 32e7a4b92b
commit c51e5ce452
4 changed files with 10 additions and 4 deletions

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@@ -73,6 +73,7 @@ features! {
/// * Zihintpause: `"zihintpause"` /// * Zihintpause: `"zihintpause"`
/// * Zihpm: `"zihpm"` /// * Zihpm: `"zihpm"`
/// * Zimop: `"zimop"` /// * Zimop: `"zimop"`
/// * Zabha: `"zabha"`
/// * Zacas: `"zacas"` /// * Zacas: `"zacas"`
/// * Zawrs: `"zawrs"` /// * Zawrs: `"zawrs"`
/// * Zfa: `"zfa"` /// * Zfa: `"zfa"`
@@ -195,6 +196,8 @@ features! {
/// "Zaamo" Extension for Atomic Memory Operations /// "Zaamo" Extension for Atomic Memory Operations
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs"; @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
/// "Zawrs" Extension for Wait-on-Reservation-Set Instructions /// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zabha: "zabha";
/// "Zabha" Extension for Byte and Halfword Atomic Memory Operations
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas"; @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
/// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions /// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam"; @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";

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@@ -10,13 +10,13 @@ use super::super::riscv::imply_features;
use super::auxvec; use super::auxvec;
use crate::detect::{Feature, bit, cache}; use crate::detect::{Feature, bit, cache};
// See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/prctl.h?h=v6.15> // See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/prctl.h?h=v6.16>
// for runtime status query constants. // for runtime status query constants.
const PR_RISCV_V_GET_CONTROL: libc::c_int = 70; const PR_RISCV_V_GET_CONTROL: libc::c_int = 70;
const PR_RISCV_V_VSTATE_CTRL_ON: libc::c_int = 2; const PR_RISCV_V_VSTATE_CTRL_ON: libc::c_int = 2;
const PR_RISCV_V_VSTATE_CTRL_CUR_MASK: libc::c_int = 3; const PR_RISCV_V_VSTATE_CTRL_CUR_MASK: libc::c_int = 3;
// See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwprobe.h?h=v6.15> // See <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwprobe.h?h=v6.16>
// for riscv_hwprobe struct and hardware probing constants. // for riscv_hwprobe struct and hardware probing constants.
#[repr(C)] #[repr(C)]
@@ -98,6 +98,7 @@ const RISCV_HWPROBE_EXT_ZVFBFWMA: u64 = 1 << 54;
const RISCV_HWPROBE_EXT_ZICBOM: u64 = 1 << 55; const RISCV_HWPROBE_EXT_ZICBOM: u64 = 1 << 55;
const RISCV_HWPROBE_EXT_ZAAMO: u64 = 1 << 56; const RISCV_HWPROBE_EXT_ZAAMO: u64 = 1 << 56;
const RISCV_HWPROBE_EXT_ZALRSC: u64 = 1 << 57; const RISCV_HWPROBE_EXT_ZALRSC: u64 = 1 << 57;
const RISCV_HWPROBE_EXT_ZABHA: u64 = 1 << 58;
const RISCV_HWPROBE_KEY_CPUPERF_0: i64 = 5; const RISCV_HWPROBE_KEY_CPUPERF_0: i64 = 5;
const RISCV_HWPROBE_MISALIGNED_FAST: u64 = 3; const RISCV_HWPROBE_MISALIGNED_FAST: u64 = 3;
@@ -138,7 +139,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
// Use auxiliary vector to enable single-letter ISA extensions. // Use auxiliary vector to enable single-letter ISA extensions.
// The values are part of the platform-specific [asm/hwcap.h][hwcap] // The values are part of the platform-specific [asm/hwcap.h][hwcap]
// //
// [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.15 // [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.16
let auxv = auxvec::auxv().expect("read auxvec"); // should not fail on RISC-V platform let auxv = auxvec::auxv().expect("read auxvec"); // should not fail on RISC-V platform
let mut has_i = bit::test(auxv.hwcap, (b'i' - b'a').into()); let mut has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
#[allow(clippy::eq_op)] #[allow(clippy::eq_op)]
@@ -233,6 +234,7 @@ pub(crate) fn detect_features() -> cache::Initializer {
enable_feature(Feature::zalrsc, test(RISCV_HWPROBE_EXT_ZALRSC)); enable_feature(Feature::zalrsc, test(RISCV_HWPROBE_EXT_ZALRSC));
enable_feature(Feature::zaamo, test(RISCV_HWPROBE_EXT_ZAAMO)); enable_feature(Feature::zaamo, test(RISCV_HWPROBE_EXT_ZAAMO));
enable_feature(Feature::zawrs, test(RISCV_HWPROBE_EXT_ZAWRS)); enable_feature(Feature::zawrs, test(RISCV_HWPROBE_EXT_ZAWRS));
enable_feature(Feature::zabha, test(RISCV_HWPROBE_EXT_ZABHA));
enable_feature(Feature::zacas, test(RISCV_HWPROBE_EXT_ZACAS)); enable_feature(Feature::zacas, test(RISCV_HWPROBE_EXT_ZACAS));
enable_feature(Feature::ztso, test(RISCV_HWPROBE_EXT_ZTSO)); enable_feature(Feature::ztso, test(RISCV_HWPROBE_EXT_ZTSO));

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@@ -90,7 +90,7 @@ pub(crate) fn imply_features(mut value: cache::Initializer) -> cache::Initialize
group!(zks == zbkb & zbkc & zbkx & zksed & zksh); group!(zks == zbkb & zbkc & zbkx & zksed & zksh);
group!(zk == zkn & zkr & zkt); group!(zk == zkn & zkr & zkt);
imply!(zacas => zaamo); imply!(zabha | zacas => zaamo);
group!(a == zalrsc & zaamo); group!(a == zalrsc & zaamo);
group!(b == zba & zbb & zbs); group!(b == zba & zbb & zbs);

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@@ -242,6 +242,7 @@ fn riscv_linux() {
println!("zalrsc: {}", is_riscv_feature_detected!("zalrsc")); println!("zalrsc: {}", is_riscv_feature_detected!("zalrsc"));
println!("zaamo: {}", is_riscv_feature_detected!("zaamo")); println!("zaamo: {}", is_riscv_feature_detected!("zaamo"));
println!("zawrs: {}", is_riscv_feature_detected!("zawrs")); println!("zawrs: {}", is_riscv_feature_detected!("zawrs"));
println!("zabha: {}", is_riscv_feature_detected!("zabha"));
println!("zacas: {}", is_riscv_feature_detected!("zacas")); println!("zacas: {}", is_riscv_feature_detected!("zacas"));
println!("zam: {}", is_riscv_feature_detected!("zam")); println!("zam: {}", is_riscv_feature_detected!("zam"));
println!("ztso: {}", is_riscv_feature_detected!("ztso")); println!("ztso: {}", is_riscv_feature_detected!("ztso"));