Auto merge of #132472 - taiki-e:sparc-asm, r=Amanieu
Basic inline assembly support for SPARC and SPARC64
This implements asm_experimental_arch (tracking issue https://github.com/rust-lang/rust/issues/93335) for SPARC and SPARC64.
This PR includes:
- General-purpose registers `r[0-31]` (`reg` register class, LLVM/GCC constraint `r`)
Supported types: i8, i16, i32, i64 (SPARC64-only)
Aliases: `g[0-7]` (`r[0-7]`), `o[0-7]` (`r[8-15]`), `l[0-7]` (`r[16-23]`), `i[0-7]` (`r[24-31]`)
- `y` register (clobber-only, needed for clobber_abi)
- preserves_flags: Integer condition codes (`icc`, `xcc`) and floating-point condition codes (`fcc*`)
The following are *not* included:
- 64-bit integer support on SPARC-V8+'s global or out registers (`g[0-7]`, `o[0-7]`): GCC's `h` constraint (it seems that there is no corresponding constraint in LLVM?)
- Floating-point registers (LLVM/GCC constraint `e`/`f`):
I initially tried to implement this, but postponed it for now because there seemed to be several parts in LLVM that behaved differently than in the LangRef's description.
- clobber_abi: Support for floating-point registers is needed.
Refs:
- LLVM
- Reserved registers https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp#L52
- Register definitions https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/SparcRegisterInfo.td
- Supported constraints https://llvm.org/docs/LangRef.html#supported-constraint-code-list
- GCC
- Reserved registers 63b6967b06/gcc/config/sparc/sparc.h (L633-L658)
- Supported constraints https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html
- SPARC ISA/ABI
- (64-bit ISA) The SPARC Architecture Manual, Version 9
(32-bit ISA) The SPARC Architecture Manual, Version 8
(64-bit ABI) System V Application Binary Interface SPARC Version 9 Processor Supplement, Rev 1.35
(32-bit ABI) System V Application Binary Interface SPARC Processor Supplement, Third Edition
The above docs can be downloaded from https://sparc.org/technical-documents
- (32-bit V8+ ABI) The V8+ Technical Specification
https://temlib.org/pub/SparcStation/Standards/V8plus.pdf
cc `@thejpster` (sparc-unknown-none-elf target maintainer)
(AFAIK, other sparc/sprac64 targets don't have target maintainers)
r? `@Amanieu`
`@rustbot` label +O-SPARC +A-inline-assembly
This commit is contained in:
bors
@@ -191,6 +191,7 @@ mod nvptx;
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mod powerpc;
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mod riscv;
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mod s390x;
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mod sparc;
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mod spirv;
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mod wasm;
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mod x86;
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@@ -209,6 +210,7 @@ pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use s390x::{S390xInlineAsmReg, S390xInlineAsmRegClass};
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pub use sparc::{SparcInlineAsmReg, SparcInlineAsmRegClass};
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pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
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pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
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pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
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@@ -230,6 +232,8 @@ pub enum InlineAsmArch {
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PowerPC,
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PowerPC64,
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S390x,
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Sparc,
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Sparc64,
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SpirV,
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Wasm32,
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Wasm64,
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@@ -260,6 +264,8 @@ impl FromStr for InlineAsmArch {
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"mips" | "mips32r6" => Ok(Self::Mips),
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"mips64" | "mips64r6" => Ok(Self::Mips64),
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"s390x" => Ok(Self::S390x),
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"sparc" => Ok(Self::Sparc),
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"sparc64" => Ok(Self::Sparc64),
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"spirv" => Ok(Self::SpirV),
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"wasm32" => Ok(Self::Wasm32),
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"wasm64" => Ok(Self::Wasm64),
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@@ -286,6 +292,7 @@ pub enum InlineAsmReg {
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LoongArch(LoongArchInlineAsmReg),
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Mips(MipsInlineAsmReg),
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S390x(S390xInlineAsmReg),
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Sparc(SparcInlineAsmReg),
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SpirV(SpirVInlineAsmReg),
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Wasm(WasmInlineAsmReg),
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Bpf(BpfInlineAsmReg),
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@@ -309,6 +316,7 @@ impl InlineAsmReg {
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Self::LoongArch(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::S390x(r) => r.name(),
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Self::Sparc(r) => r.name(),
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Self::Bpf(r) => r.name(),
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Self::Avr(r) => r.name(),
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Self::Msp430(r) => r.name(),
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@@ -329,6 +337,7 @@ impl InlineAsmReg {
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Self::LoongArch(r) => InlineAsmRegClass::LoongArch(r.reg_class()),
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Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
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Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()),
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Self::Sparc(r) => InlineAsmRegClass::Sparc(r.reg_class()),
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Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
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Self::Avr(r) => InlineAsmRegClass::Avr(r.reg_class()),
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Self::Msp430(r) => InlineAsmRegClass::Msp430(r.reg_class()),
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@@ -361,6 +370,9 @@ impl InlineAsmReg {
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Self::Mips(MipsInlineAsmReg::parse(name)?)
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}
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InlineAsmArch::S390x => Self::S390x(S390xInlineAsmReg::parse(name)?),
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InlineAsmArch::Sparc | InlineAsmArch::Sparc64 => {
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Self::Sparc(SparcInlineAsmReg::parse(name)?)
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}
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InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmReg::parse(name)?),
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InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {
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Self::Wasm(WasmInlineAsmReg::parse(name)?)
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@@ -393,6 +405,7 @@ impl InlineAsmReg {
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}
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Self::Mips(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::S390x(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Sparc(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Bpf(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Avr(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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Self::Msp430(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
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@@ -420,6 +433,7 @@ impl InlineAsmReg {
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Self::LoongArch(r) => r.emit(out, arch, modifier),
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Self::Mips(r) => r.emit(out, arch, modifier),
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Self::S390x(r) => r.emit(out, arch, modifier),
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Self::Sparc(r) => r.emit(out, arch, modifier),
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Self::Bpf(r) => r.emit(out, arch, modifier),
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Self::Avr(r) => r.emit(out, arch, modifier),
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Self::Msp430(r) => r.emit(out, arch, modifier),
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@@ -440,6 +454,7 @@ impl InlineAsmReg {
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Self::LoongArch(_) => cb(self),
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Self::Mips(_) => cb(self),
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Self::S390x(r) => r.overlapping_regs(|r| cb(Self::S390x(r))),
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Self::Sparc(_) => cb(self),
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Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
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Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))),
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Self::Msp430(_) => cb(self),
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@@ -463,6 +478,7 @@ pub enum InlineAsmRegClass {
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LoongArch(LoongArchInlineAsmRegClass),
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Mips(MipsInlineAsmRegClass),
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S390x(S390xInlineAsmRegClass),
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Sparc(SparcInlineAsmRegClass),
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SpirV(SpirVInlineAsmRegClass),
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Wasm(WasmInlineAsmRegClass),
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Bpf(BpfInlineAsmRegClass),
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@@ -487,6 +503,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::S390x(r) => r.name(),
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Self::Sparc(r) => r.name(),
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Self::SpirV(r) => r.name(),
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Self::Wasm(r) => r.name(),
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Self::Bpf(r) => r.name(),
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@@ -513,6 +530,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::LoongArch),
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Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
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Self::S390x(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::S390x),
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Self::Sparc(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Sparc),
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Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
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Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
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Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
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@@ -542,6 +560,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.suggest_modifier(arch, ty),
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Self::Mips(r) => r.suggest_modifier(arch, ty),
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Self::S390x(r) => r.suggest_modifier(arch, ty),
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Self::Sparc(r) => r.suggest_modifier(arch, ty),
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Self::SpirV(r) => r.suggest_modifier(arch, ty),
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Self::Wasm(r) => r.suggest_modifier(arch, ty),
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Self::Bpf(r) => r.suggest_modifier(arch, ty),
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@@ -571,6 +590,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.default_modifier(arch),
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Self::Mips(r) => r.default_modifier(arch),
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Self::S390x(r) => r.default_modifier(arch),
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Self::Sparc(r) => r.default_modifier(arch),
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Self::SpirV(r) => r.default_modifier(arch),
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Self::Wasm(r) => r.default_modifier(arch),
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Self::Bpf(r) => r.default_modifier(arch),
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@@ -599,6 +619,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.supported_types(arch),
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Self::Mips(r) => r.supported_types(arch),
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Self::S390x(r) => r.supported_types(arch),
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Self::Sparc(r) => r.supported_types(arch),
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Self::SpirV(r) => r.supported_types(arch),
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Self::Wasm(r) => r.supported_types(arch),
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Self::Bpf(r) => r.supported_types(arch),
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@@ -632,6 +653,9 @@ impl InlineAsmRegClass {
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Self::Mips(MipsInlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::S390x => Self::S390x(S390xInlineAsmRegClass::parse(name)?),
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InlineAsmArch::Sparc | InlineAsmArch::Sparc64 => {
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Self::Sparc(SparcInlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(name)?),
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InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {
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Self::Wasm(WasmInlineAsmRegClass::parse(name)?)
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@@ -658,6 +682,7 @@ impl InlineAsmRegClass {
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Self::LoongArch(r) => r.valid_modifiers(arch),
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Self::Mips(r) => r.valid_modifiers(arch),
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Self::S390x(r) => r.valid_modifiers(arch),
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Self::Sparc(r) => r.valid_modifiers(arch),
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Self::SpirV(r) => r.valid_modifiers(arch),
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Self::Wasm(r) => r.valid_modifiers(arch),
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Self::Bpf(r) => r.valid_modifiers(arch),
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@@ -843,6 +868,11 @@ pub fn allocatable_registers(
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s390x::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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}
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InlineAsmArch::Sparc | InlineAsmArch::Sparc64 => {
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let mut map = sparc::regclass_map();
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sparc::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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}
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InlineAsmArch::SpirV => {
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let mut map = spirv::regclass_map();
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spirv::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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