rust-lang/rust
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge commit 'ef07e8e60f994ec014d049a95591426fb92ebb79' into sync_cg_clif-2023-04-29

Browse Source
This commit is contained in:
bjorn3
2023-04-29 12:00:43 +00:00
parent f2299490c1 ef07e8e60f
commit a8697f9565
51 changed files with 1469 additions and 675 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
View File

@@ -51,17 +51,13 @@ fn report_atomic_type_validation_error<'tcx>(
fx.bcx.ins().trap(TrapCode::UnreachableCodeReached);
}
pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx>) -> Option<Type> {
pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx>) -> Type {
let (element, count) = match layout.abi {
Abi::Vector { element, count } => (element, count),
_ => unreachable!(),
};
match scalar_to_clif_type(tcx, element).by(u32::try_from(count).unwrap()) {
// Cranelift currently only implements icmp for 128bit vectors.
Some(vector_ty) if vector_ty.bits() == 128 => Some(vector_ty),
_ => None,
}
scalar_to_clif_type(tcx, element).by(u32::try_from(count).unwrap()).unwrap()
}
fn simd_for_each_lane<'tcx>(
@@ -1107,8 +1103,8 @@ fn codegen_regular_intrinsic_call<'tcx>(
fx.bcx.ins().call_indirect(f_sig, f, &[data]);
let layout = ret.layout();
let ret_val = CValue::const_val(fx, layout, ty::ScalarInt::null(layout.size));
let layout = fx.layout_of(fx.tcx.types.i32);
let ret_val = CValue::by_val(fx.bcx.ins().iconst(types::I32, 0), layout);
ret.write_cvalue(fx, ret_val);
}

2
compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs
View File

@@ -253,7 +253,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
}
ret.write_cvalue(fx, base);
let ret_lane = ret.place_field(fx, FieldIdx::new(idx.try_into().unwrap()));
let ret_lane = ret.place_lane(fx, idx.try_into().unwrap());
ret_lane.write_cvalue(fx, val);
}