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Rollup merge of #145417 - a4lg:riscv-arch-platform-guide-ch2, r=Amanieu

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std_detect: RISC-V platform guide documentation

This is practically a revert of a revert, making the commit e907456b2e10622ccd854a3bba8d02ce170b5dbb on `stdarch` come around again with minor fixes, enhancements and adjustments.

An excerpt from the original commit message follows:

Since there's no architectural feature detection on RISC-V (unlike `CPUID` on x86 architectures and some system registers on Arm/AArch64), runtime feature detection entirely depends on the platform-specific facility.

As a result, availability of each feature heavily depends on the platform and its version.

To help users make a decision for feature checking on a RISC-V system, this commit adds a platform guide with minimum supported platform versions.
This commit is contained in:
Jacob Pratt
2025-08-20 00:45:57 -04:00
committed by GitHub
parent 5a0c9386a2 bec399e5a0
commit 9261fcf159
1 changed files with 114 additions and 83 deletions
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197
library/std_detect/src/detect/arch/riscv.rs
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@@ -37,90 +37,121 @@ features! {
/// ///
/// # Unprivileged Specification /// # Unprivileged Specification
/// ///
/// The supported ratified RISC-V instruction sets are as follows: /// The supported ratified RISC-V instruction sets are as follows (OS
/// columns denote runtime feature detection support with or without the
/// minimum supported version):
/// ///
/// * RV32E: `"rv32e"` /// | Literal | Base | Linux |
/// * RV32I: `"rv32i"` /// |:---------- |:------- |:---------- |
/// * RV64I: `"rv64i"` /// | `"rv32e"` | RV32E | No |
/// * A: `"a"` /// | `"rv32i"` | RV32I | Yes [^ima] |
/// * Zaamo: `"zaamo"` /// | `"rv64i"` | RV64I | Yes [^ima] |
/// * Zalrsc: `"zalrsc"` ///
/// * B: `"b"` /// | Literal | Extension | Linux |
/// * Zba: `"zba"` /// |:--------------- |:----------- |:------------------- |
/// * Zbb: `"zbb"` /// | `"a"` | A | Yes [^ima] |
/// * Zbs: `"zbs"` /// | `"b"` | B | 6.5 |
/// * C: `"c"` /// | `"c"` | C | Yes |
/// * Zca: `"zca"` /// | `"d"` | D | Yes |
/// * Zcd: `"zcd"` (if D is enabled) /// | `"f"` | F | Yes |
/// * Zcf: `"zcf"` (if F is enabled on RV32) /// | `"m"` | M | Yes [^ima] |
/// * D: `"d"` /// | `"q"` | Q | No |
/// * F: `"f"` /// | `"v"` | V | 6.5 |
/// * M: `"m"` /// | `"zaamo"` | Zaamo | 6.15 [^ima] [^dep] |
/// * Q: `"q"` /// | `"zabha"` | Zabha | 6.16 |
/// * V: `"v"` /// | `"zacas"` | Zacas | 6.8 |
/// * Zve32x: `"zve32x"` /// | `"zalrsc"` | Zalrsc | 6.15 [^ima] [^dep] |
/// * Zve32f: `"zve32f"` /// | `"zawrs"` | Zawrs | 6.11 |
/// * Zve64x: `"zve64x"` /// | `"zba"` | Zba | 6.5 |
/// * Zve64f: `"zve64f"` /// | `"zbb"` | Zbb | 6.5 |
/// * Zve64d: `"zve64d"` /// | `"zbc"` | Zbc | 6.8 |
/// * Zicbom: `"zicbom"` /// | `"zbkb"` | Zbkb | 6.8 |
/// * Zicboz: `"zicboz"` /// | `"zbkc"` | Zbkc | 6.8 |
/// * Zicntr: `"zicntr"` /// | `"zbkx"` | Zbkx | 6.8 |
/// * Zicond: `"zicond"` /// | `"zbs"` | Zbs | 6.5 |
/// * Zicsr: `"zicsr"` /// | `"zca"` | Zca | 6.11 [^dep] |
/// * Zifencei: `"zifencei"` /// | `"zcb"` | Zcb | 6.11 |
/// * Zihintntl: `"zihintntl"` /// | `"zcd"` | Zcd | 6.11 [^dep] |
/// * Zihintpause: `"zihintpause"` /// | `"zcf"` | Zcf | 6.11 [^dep] |
/// * Zihpm: `"zihpm"` /// | `"zcmop"` | Zcmop | 6.11 |
/// * Zimop: `"zimop"` /// | `"zdinx"` | Zdinx | No |
/// * Zabha: `"zabha"` /// | `"zfa"` | Zfa | 6.8 |
/// * Zacas: `"zacas"` /// | `"zfbfmin"` | Zfbfmin | 6.15 |
/// * Zawrs: `"zawrs"` /// | `"zfh"` | Zfh | 6.8 |
/// * Zfa: `"zfa"` /// | `"zfhmin"` | Zfhmin | 6.8 |
/// * Zfbfmin: `"zfbfmin"` /// | `"zfinx"` | Zfinx | No |
/// * Zfh: `"zfh"` /// | `"zhinx"` | Zhinx | No |
/// * Zfhmin: `"zfhmin"` /// | `"zhinxmin"` | Zhinxmin | No |
/// * Zfinx: `"zfinx"` /// | `"zicbom"` | Zicbom | 6.15 |
/// * Zdinx: `"zdinx"` /// | `"zicboz"` | Zicboz | 6.7 |
/// * Zhinx: `"zhinx"` /// | `"zicntr"` | Zicntr | 6.15 [^ima] [^cntr] |
/// * Zhinxmin: `"zhinxmin"` /// | `"zicond"` | Zicond | 6.8 |
/// * Zcb: `"zcb"` /// | `"zicsr"` | Zicsr | No [^ima] [^dep] |
/// * Zcmop: `"zcmop"` /// | `"zifencei"` | Zifencei | No [^ima] |
/// * Zbc: `"zbc"` /// | `"zihintntl"` | Zihintntl | 6.8 |
/// * Zbkb: `"zbkb"` /// | `"zihintpause"` | Zihintpause | 6.10 |
/// * Zbkc: `"zbkc"` /// | `"zihpm"` | Zihpm | 6.15 [^cntr] |
/// * Zbkx: `"zbkx"` /// | `"zimop"` | Zimop | 6.11 |
/// * Zk: `"zk"` /// | `"zk"` | Zk | No [^zkr] |
/// * Zkn: `"zkn"` /// | `"zkn"` | Zkn | 6.8 |
/// * Zknd: `"zknd"` /// | `"zknd"` | Zknd | 6.8 |
/// * Zkne: `"zkne"` /// | `"zkne"` | Zkne | 6.8 |
/// * Zknh: `"zknh"` /// | `"zknh"` | Zknh | 6.8 |
/// * Zkr: `"zkr"` /// | `"zkr"` | Zkr | No [^zkr] |
/// * Zks: `"zks"` /// | `"zks"` | Zks | 6.8 |
/// * Zksed: `"zksed"` /// | `"zksed"` | Zksed | 6.8 |
/// * Zksh: `"zksh"` /// | `"zksh"` | Zksh | 6.8 |
/// * Zkt: `"zkt"` /// | `"zkt"` | Zkt | 6.8 |
/// * Zvbb: `"zvbb"` /// | `"ztso"` | Ztso | 6.8 |
/// * Zvbc: `"zvbc"` /// | `"zvbb"` | Zvbb | 6.8 |
/// * Zvfbfmin: `"zvfbfmin"` /// | `"zvbc"` | Zvbc | 6.8 |
/// * Zvfbfwma: `"zvfbfwma"` /// | `"zve32f"` | Zve32f | 6.11 [^dep] |
/// * Zvfh: `"zvfh"` /// | `"zve32x"` | Zve32x | 6.11 [^dep] |
/// * Zvfhmin: `"zvfhmin"` /// | `"zve64d"` | Zve64d | 6.11 [^dep] |
/// * Zvkb: `"zvkb"` /// | `"zve64f"` | Zve64f | 6.11 [^dep] |
/// * Zvkg: `"zvkg"` /// | `"zve64x"` | Zve64x | 6.11 [^dep] |
/// * Zvkn: `"zvkn"` /// | `"zvfbfmin"` | Zvfbfmin | 6.15 |
/// * Zvkned: `"zvkned"` /// | `"zvfbfwma"` | Zvfbfwma | 6.15 |
/// * Zvknha: `"zvknha"` /// | `"zvfh"` | Zvfh | 6.8 |
/// * Zvknhb: `"zvknhb"` /// | `"zvfhmin"` | Zvfhmin | 6.8 |
/// * Zvknc: `"zvknc"` /// | `"zvkb"` | Zvkb | 6.8 |
/// * Zvkng: `"zvkng"` /// | `"zvkg"` | Zvkg | 6.8 |
/// * Zvks: `"zvks"` /// | `"zvkn"` | Zvkn | 6.8 |
/// * Zvksed: `"zvksed"` /// | `"zvknc"` | Zvknc | 6.8 |
/// * Zvksh: `"zvksh"` /// | `"zvkned"` | Zvkned | 6.8 |
/// * Zvksc: `"zvksc"` /// | `"zvkng"` | Zvkng | 6.8 |
/// * Zvksg: `"zvksg"` /// | `"zvknha"` | Zvknha | 6.8 |
/// * Zvkt: `"zvkt"` /// | `"zvknhb"` | Zvknhb | 6.8 |
/// * Ztso: `"ztso"` /// | `"zvks"` | Zvks | 6.8 |
/// | `"zvksc"` | Zvksc | 6.8 |
/// | `"zvksed"` | Zvksed | 6.8 |
/// | `"zvksg"` | Zvksg | 6.8 |
/// | `"zvksh"` | Zvksh | 6.8 |
/// | `"zvkt"` | Zvkt | 6.8 |
///
/// [^ima]: Or enabled when the IMA base behavior is detected on the Linux
/// kernel version 6.4 or later (for bases, the only matching one -- either
/// `"rv32i"` or `"rv64i"` -- is enabled).
///
/// [^cntr]: Even if this extension is available, it does not necessarily
/// mean all performance counters are accessible.
/// For example, accesses to all performance counters except `time`
/// (wall-clock) are blocked by default on the Linux kernel
/// version 6.6 or later.
/// Also beware that, even if performance counters like `cycle` and
/// `instret` are accessible, their value can be unreliable (e.g. returning
/// the constant value) under certain circumstances.
///
/// [^dep]: Or enabled as a dependency of another extension (a superset)
/// even if runtime detection of this feature itself is not supported (as
/// long as the runtime detection of the superset is supported).
///
/// [^zkr]: Linux does not report existence of this extension even if
/// supported by the hardware mainly because the `seed` CSR on the Zkr
/// extension (which provides hardware-based randomness) is normally
/// inaccessible from the user mode.
/// For the Zk extension features except this CSR, check existence of both
/// `"zkn"` and `"zkt"` features instead.
/// ///
/// There's also bases and extensions marked as standard instruction set, /// There's also bases and extensions marked as standard instruction set,
/// but they are in frozen or draft state. These instruction sets are also /// but they are in frozen or draft state. These instruction sets are also