Add asm! support for mips64
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@@ -176,6 +176,7 @@ pub enum InlineAsmArch {
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Nvptx64,
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Hexagon,
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Mips,
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Mips64,
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}
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impl FromStr for InlineAsmArch {
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@@ -192,6 +193,7 @@ impl FromStr for InlineAsmArch {
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"nvptx64" => Ok(Self::Nvptx64),
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"hexagon" => Ok(Self::Hexagon),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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_ => Err(()),
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}
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}
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@@ -259,7 +261,7 @@ impl InlineAsmReg {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Mips => {
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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})
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@@ -409,7 +411,9 @@ impl InlineAsmRegClass {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
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}
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})
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})
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}
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@@ -565,7 +569,7 @@ pub fn allocatable_registers(
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hexagon::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Mips => {
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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let mut map = mips::regclass_map();
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mips::fill_reg_map(arch, has_feature, target, &mut map);
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map
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