Add f16 inline ASM support for 32-bit ARM
This commit is contained in:
@@ -47,16 +47,18 @@ impl ArmInlineAsmRegClass {
|
||||
_arch: InlineAsmArch,
|
||||
) -> &'static [(InlineAsmType, Option<Symbol>)] {
|
||||
match self {
|
||||
Self::reg => types! { _: I8, I16, I32, F32; },
|
||||
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; },
|
||||
Self::reg => types! { _: I8, I16, I32, F16, F32; },
|
||||
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F16, F32; },
|
||||
Self::dreg_low16 | Self::dreg_low8 => types! {
|
||||
vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
|
||||
vfp2: I64, F64;
|
||||
neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2);
|
||||
},
|
||||
Self::dreg => types! {
|
||||
d32: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
|
||||
d32: I64, F64;
|
||||
neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2);
|
||||
},
|
||||
Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! {
|
||||
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
|
||||
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF16(8), VecF32(4);
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user