llvm: nvptx: Layout update to match LLVM

LLVM upstream switched layouts to support 256-bit vector load/store.
2025-09-02 18:43:48 +00:00
parent a2c8b0b92c
commit 5d9f8fcd3e
2 changed files with 5 additions and 1 deletions
--- a/compiler/rustc_codegen_llvm/src/context.rs
+++ b/compiler/rustc_codegen_llvm/src/context.rs
@@ -217,6 +217,10 @@ pub(crate) unsafe fn create_module<'ll>(
            // LLVM 22.0 updated the default layout on avr: https://github.com/llvm/llvm-project/pull/153010
            target_data_layout = target_data_layout.replace("n8:16", "n8")
        }
+        if sess.target.arch == "nvptx64" {
+            // LLVM 22 updated the NVPTX layout to indicate 256-bit vector load/store: https://github.com/llvm/llvm-project/pull/155198
+            target_data_layout = target_data_layout.replace("-i256:256", "");
+        }
    }

    // Ensure the data-layout values hardcoded remain the defaults.