convert _mm256_cmp_epu8_mask to const generics
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committed by
Amanieu d'Antras
parent
98c070c120
commit
5d8ef1ba70
@@ -3835,17 +3835,13 @@ pub unsafe fn _mm512_mask_cmp_epu8_mask<const IMM8: i32>(
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/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_epu8_mask&expand=731)
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#[inline]
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#[target_feature(enable = "avx512bw,avx512vl")]
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#[rustc_args_required_const(2)]
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#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))]
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pub unsafe fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i, imm8: i32) -> __mmask32 {
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
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pub unsafe fn _mm256_cmp_epu8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
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static_assert_imm3!(IMM8);
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let a = a.as_u8x32();
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let b = b.as_u8x32();
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macro_rules! call {
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($imm3:expr) => {
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vpcmpub256(a, b, $imm3, 0b11111111_11111111_11111111_11111111)
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};
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}
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let r = constify_imm3!(imm8, call);
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let r = vpcmpub256(a, b, IMM8, 0b11111111_11111111_11111111_11111111);
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transmute(r)
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}
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@@ -13499,7 +13495,7 @@ mod tests {
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unsafe fn test_mm256_cmp_epu8_mask() {
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let a = _mm256_set1_epi8(0);
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let b = _mm256_set1_epi8(1);
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let m = _mm256_cmp_epu8_mask(a, b, _MM_CMPINT_LT);
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let m = _mm256_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
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assert_eq!(m, 0b11111111_11111111_11111111_11111111);
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}
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