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Replace target.target with target and target.ptr_width with target.pointer_width

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Preparation for a subsequent change that replaces
rustc_target::config::Config with its wrapped Target.

On its own, this commit breaks the build. I don't like making
build-breaking commits, but in this instance I believe that it
makes review easier, as the "real" changes of this PR can be
seen much more easily.

Result of running:

find compiler/ -type f -exec sed -i -e 's/target\.target\([)\.,; ]\)/target\1/g' {} \;
find compiler/ -type f -exec sed -i -e 's/target\.target$/target/g' {} \;
find compiler/ -type f -exec sed -i -e 's/target.ptr_width/target.pointer_width/g' {} \;
./x.py fmt
This commit is contained in:
est31
2020-10-15 11:44:00 +02:00
parent 0d1aa1e034
commit 4fa5578774
50 changed files with 224 additions and 240 deletions
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2
compiler/rustc_codegen_ssa/src/mir/block.rs
View File

@@ -872,7 +872,7 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
let string = match ty.kind() {
ty::Uint(_) => value.to_string(),
ty::Int(int_ty) => {
match int_ty.normalize(bx.tcx().sess.target.ptr_width) {
match int_ty.normalize(bx.tcx().sess.target.pointer_width) {
ast::IntTy::I8 => (value as i8).to_string(),
ast::IntTy::I16 => (value as i16).to_string(),
ast::IntTy::I32 => (value as i32).to_string(),

8
compiler/rustc_codegen_ssa/src/mir/intrinsic.rs
View File

@@ -580,8 +580,12 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
// stuffs.
fn int_type_width_signed(ty: Ty<'_>, tcx: TyCtxt<'_>) -> Option<(u64, bool)> {
match ty.kind() {
ty::Int(t) => Some((t.bit_width().unwrap_or(u64::from(tcx.sess.target.ptr_width)), true)),
ty::Uint(t) => Some((t.bit_width().unwrap_or(u64::from(tcx.sess.target.ptr_width)), false)),
ty::Int(t) => {
Some((t.bit_width().unwrap_or(u64::from(tcx.sess.target.pointer_width)), true))
}
ty::Uint(t) => {
Some((t.bit_width().unwrap_or(u64::from(tcx.sess.target.pointer_width)), false))
}
_ => None,
}
}

4
compiler/rustc_codegen_ssa/src/mir/place.rs
View File

@@ -346,8 +346,8 @@ impl<'a, 'tcx, V: CodegenObject> PlaceRef<'tcx, V> {
..
} => {
if variant_index != dataful_variant {
if bx.cx().sess().target.target.arch == "arm"
|| bx.cx().sess().target.target.arch == "aarch64"
if bx.cx().sess().target.arch == "arm"
|| bx.cx().sess().target.arch == "aarch64"
{
// FIXME(#34427): as workaround for LLVM bug on ARM,
// use memset of 0 before assigning niche value.