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Add new Tier-3 targets: loongarch32-unknown-none*

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MCP: https://github.com/rust-lang/compiler-team/issues/865
This commit is contained in:
WANG Rui
2025-01-09 20:35:49 +08:00
parent 27f8efbae2
commit 38d69c3f57
30 changed files with 149 additions and 33 deletions
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14
compiler/rustc_target/src/asm/mod.rs
View File

@@ -226,6 +226,7 @@ pub enum InlineAsmArch {
RiscV64,
Nvptx64,
Hexagon,
LoongArch32,
LoongArch64,
Mips,
Mips64,
@@ -260,6 +261,7 @@ impl FromStr for InlineAsmArch {
"powerpc" => Ok(Self::PowerPC),
"powerpc64" => Ok(Self::PowerPC64),
"hexagon" => Ok(Self::Hexagon),
"loongarch32" => Ok(Self::LoongArch32),
"loongarch64" => Ok(Self::LoongArch64),
"mips" | "mips32r6" => Ok(Self::Mips),
"mips64" | "mips64r6" => Ok(Self::Mips64),
@@ -365,7 +367,9 @@ impl InlineAsmReg {
Self::PowerPC(PowerPCInlineAsmReg::parse(name)?)
}
InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmReg::parse(name)?),
InlineAsmArch::LoongArch64 => Self::LoongArch(LoongArchInlineAsmReg::parse(name)?),
InlineAsmArch::LoongArch32 | InlineAsmArch::LoongArch64 => {
Self::LoongArch(LoongArchInlineAsmReg::parse(name)?)
}
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmReg::parse(name)?)
}
@@ -652,7 +656,9 @@ impl InlineAsmRegClass {
Self::PowerPC(PowerPCInlineAsmRegClass::parse(name)?)
}
InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmRegClass::parse(name)?),
InlineAsmArch::LoongArch64 => Self::LoongArch(LoongArchInlineAsmRegClass::parse(name)?),
InlineAsmArch::LoongArch32 | InlineAsmArch::LoongArch64 => {
Self::LoongArch(LoongArchInlineAsmRegClass::parse(name)?)
}
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmRegClass::parse(name)?)
}
@@ -860,7 +866,7 @@ pub fn allocatable_registers(
hexagon::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
map
}
InlineAsmArch::LoongArch64 => {
InlineAsmArch::LoongArch32 | InlineAsmArch::LoongArch64 => {
let mut map = loongarch::regclass_map();
loongarch::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
map
@@ -992,7 +998,7 @@ impl InlineAsmClobberAbi {
"C" | "system" => Ok(InlineAsmClobberAbi::Avr),
_ => Err(&["C", "system"]),
},
InlineAsmArch::LoongArch64 => match name {
InlineAsmArch::LoongArch32 | InlineAsmArch::LoongArch64 => match name {
"C" | "system" => Ok(InlineAsmClobberAbi::LoongArch),
_ => Err(&["C", "system"]),
},

4
compiler/rustc_target/src/callconv/mod.rs
View File

@@ -648,7 +648,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
"amdgpu" => amdgpu::compute_abi_info(cx, self),
"arm" => arm::compute_abi_info(cx, self),
"avr" => avr::compute_abi_info(self),
"loongarch64" => loongarch::compute_abi_info(cx, self),
"loongarch32" | "loongarch64" => loongarch::compute_abi_info(cx, self),
"m68k" => m68k::compute_abi_info(self),
"csky" => csky::compute_abi_info(self),
"mips" | "mips32r6" => mips::compute_abi_info(cx, self),
@@ -691,7 +691,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
match &*spec.arch {
"x86" => x86::compute_rust_abi_info(cx, self),
"riscv32" | "riscv64" => riscv::compute_rust_abi_info(cx, self),
"loongarch64" => loongarch::compute_rust_abi_info(cx, self),
"loongarch32" | "loongarch64" => loongarch::compute_rust_abi_info(cx, self),
"aarch64" => aarch64::compute_rust_abi_info(cx, self),
_ => {}
};

3
compiler/rustc_target/src/spec/mod.rs
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@@ -1981,6 +1981,8 @@ supported_targets! {
("sparc-unknown-none-elf", sparc_unknown_none_elf),
("loongarch32-unknown-none", loongarch32_unknown_none),
("loongarch32-unknown-none-softfloat", loongarch32_unknown_none_softfloat),
("loongarch64-unknown-none", loongarch64_unknown_none),
("loongarch64-unknown-none-softfloat", loongarch64_unknown_none_softfloat),
@@ -3502,6 +3504,7 @@ impl Target {
"msp430" => (Architecture::Msp430, None),
"hexagon" => (Architecture::Hexagon, None),
"bpf" => (Architecture::Bpf, None),
"loongarch32" => (Architecture::LoongArch32, None),
"loongarch64" => (Architecture::LoongArch64, None),
"csky" => (Architecture::Csky, None),
"arm64ec" => (Architecture::Aarch64, Some(object::SubArchitecture::Arm64EC)),

29
compiler/rustc_target/src/spec/targets/loongarch32_unknown_none.rs Normal file
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@@ -0,0 +1,29 @@
use crate::spec::{
Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, TargetOptions,
};
pub(crate) fn target() -> Target {
Target {
llvm_target: "loongarch32-unknown-none".into(),
metadata: TargetMetadata {
description: Some("Freestanding/bare-metal LoongArch32".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
arch: "loongarch32".into(),
options: TargetOptions {
cpu: "generic".into(),
features: "+f,+d".into(),
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
llvm_abiname: "ilp32d".into(),
max_atomic_width: Some(32),
relocation_model: RelocModel::Static,
panic_strategy: PanicStrategy::Abort,
..Default::default()
},
}
}

30
compiler/rustc_target/src/spec/targets/loongarch32_unknown_none_softfloat.rs Normal file
View File

@@ -0,0 +1,30 @@
use crate::spec::{
Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, TargetOptions,
};
pub(crate) fn target() -> Target {
Target {
llvm_target: "loongarch32-unknown-none".into(),
metadata: TargetMetadata {
description: Some("Freestanding/bare-metal LoongArch32 softfloat".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
arch: "loongarch32".into(),
options: TargetOptions {
cpu: "generic".into(),
features: "-f,-d".into(),
abi: "softfloat".into(),
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
llvm_abiname: "ilp32s".into(),
max_atomic_width: Some(32),
relocation_model: RelocModel::Static,
panic_strategy: PanicStrategy::Abort,
..Default::default()
},
}
}

6
compiler/rustc_target/src/target_features.rs
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@@ -846,7 +846,7 @@ impl Target {
"wasm32" | "wasm64" => WASM_FEATURES,
"bpf" => BPF_FEATURES,
"csky" => CSKY_FEATURES,
"loongarch64" => LOONGARCH_FEATURES,
"loongarch32" | "loongarch64" => LOONGARCH_FEATURES,
"s390x" => IBMZ_FEATURES,
"sparc" | "sparc64" => SPARC_FEATURES,
"m68k" => M68K_FEATURES,
@@ -860,7 +860,7 @@ impl Target {
"aarch64" | "arm64ec" => AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI,
"arm" => ARM_FEATURES_FOR_CORRECT_VECTOR_ABI,
"powerpc" | "powerpc64" => POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI,
"loongarch64" => LOONGARCH_FEATURES_FOR_CORRECT_VECTOR_ABI,
"loongarch32" | "loongarch64" => LOONGARCH_FEATURES_FOR_CORRECT_VECTOR_ABI,
"riscv32" | "riscv64" => RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI,
"wasm32" | "wasm64" => WASM_FEATURES_FOR_CORRECT_VECTOR_ABI,
"s390x" => S390X_FEATURES_FOR_CORRECT_VECTOR_ABI,
@@ -1034,7 +1034,7 @@ impl Target {
_ => unreachable!(),
}
}
"loongarch64" => {
"loongarch32" | "loongarch64" => {
// LoongArch handles ABI in a very sane way, being fully explicit via `llvm_abiname`
// about what the intended ABI is.
match &*self.llvm_abiname {