add rtm cpu feature intrinsics

library/stdarch/crates/std_detect/src/detect/arch/x86.rs

@@ -74,6 +74,8 @@
 /// * `"xsaveopt"`
 /// * `"xsaves"`
 /// * `"xsavec"`
+/// * `"adx"`
+/// * `"rtm"`
 ///
 /// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
 #[macro_export]
@@ -233,6 +235,10 @@ macro_rules! is_x86_feature_detected {
         cfg!(target_feature = "adx") || $crate::detect::check_for(
             $crate::detect::Feature::adx)
     };
+    ("rtm") => {
+        cfg!(target_feature = "rtm") || $crate::detect::check_for(
+            $crate::detect::Feature::rtm)
+    };
     ($t:tt,) => {
         is_x86_feature_detected!($t);
     };
@@ -330,4 +336,6 @@ pub enum Feature {
     cmpxchg16b,
     /// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
     adx,
+    /// RTM, Intel (Restricted Transactional Memory)
+    rtm,
 }

library/stdarch/crates/std_detect/src/detect/os/x86.rs

@@ -123,6 +123,7 @@ fn detect_features() -> cache::Initializer {
         enable(proc_info_ecx, 30, Feature::rdrand);
         enable(extended_features_ebx, 18, Feature::rdseed);
         enable(extended_features_ebx, 19, Feature::adx);
+        enable(extended_features_ebx, 11, Feature::rtm);
         enable(proc_info_edx, 4, Feature::tsc);
         enable(proc_info_edx, 23, Feature::mmx);
         enable(proc_info_edx, 24, Feature::fxsr);
@@ -290,6 +291,7 @@ mod tests {
         println!("xsavec: {:?}", is_x86_feature_detected!("xsavec"));
         println!("cmpxchg16b: {:?}", is_x86_feature_detected!("cmpxchg16b"));
         println!("adx: {:?}", is_x86_feature_detected!("adx"));
+        println!("rtm: {:?}", is_x86_feature_detected!("rtm"));
     }
 
     #[test]
@@ -354,5 +356,9 @@ mod tests {
             is_x86_feature_detected!("adx"),
             information.adx(),
         );
+        assert_eq!(
+            is_x86_feature_detected!("rtm"),
+            information.rtm(),
+        );
     }
 }