2024-12-01 18:19:20 +01:00
|
|
|
warning: unexpected `cfg` condition value: `_UNEXPECTED_VALUE`
|
|
|
|
|
--> $DIR/target_feature.rs:16:10
|
|
|
|
|
|
|
|
|
|
|
LL | cfg!(target_feature = "_UNEXPECTED_VALUE");
|
|
|
|
|
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
|
|
|
|
|
|
|
= note: expected values for `target_feature` are: `10e60`
|
|
|
|
|
`2e3`
|
|
|
|
|
`3e3r1`
|
|
|
|
|
`3e3r2`
|
|
|
|
|
`3e3r3`
|
|
|
|
|
`3e7`
|
|
|
|
|
`7e10`
|
|
|
|
|
`a`
|
|
|
|
|
`aclass`
|
|
|
|
|
`adx`
|
|
|
|
|
`aes`
|
|
|
|
|
`altivec`
|
|
|
|
|
`alu32`
|
2025-03-04 20:07:25 +05:30
|
|
|
`amx-avx512`
|
2024-12-01 18:19:20 +01:00
|
|
|
`amx-bf16`
|
|
|
|
|
`amx-complex`
|
|
|
|
|
`amx-fp16`
|
2025-03-04 20:07:25 +05:30
|
|
|
`amx-fp8`
|
2024-12-01 18:19:20 +01:00
|
|
|
`amx-int8`
|
2025-03-04 20:07:25 +05:30
|
|
|
`amx-movrs`
|
|
|
|
|
`amx-tf32`
|
2024-12-01 18:19:20 +01:00
|
|
|
`amx-tile`
|
2025-03-04 20:07:25 +05:30
|
|
|
`amx-transpose`
|
2024-12-01 18:19:20 +01:00
|
|
|
`atomics`
|
|
|
|
|
`avx`
|
|
|
|
|
`avx2`
|
|
|
|
|
`avx512bf16`
|
|
|
|
|
`avx512bitalg`
|
|
|
|
|
`avx512bw`
|
|
|
|
|
`avx512cd`
|
|
|
|
|
`avx512dq`
|
|
|
|
|
`avx512f`
|
|
|
|
|
`avx512fp16`
|
|
|
|
|
`avx512ifma`
|
|
|
|
|
`avx512vbmi`
|
|
|
|
|
`avx512vbmi2`
|
|
|
|
|
`avx512vl`
|
|
|
|
|
`avx512vnni`
|
|
|
|
|
`avx512vp2intersect`
|
|
|
|
|
`avx512vpopcntdq`
|
|
|
|
|
`avxifma`
|
|
|
|
|
`avxneconvert`
|
|
|
|
|
`avxvnni`
|
|
|
|
|
`avxvnniint16`
|
|
|
|
|
`avxvnniint8`
|
|
|
|
|
`backchain`
|
|
|
|
|
`bf16`
|
|
|
|
|
`bmi1`
|
|
|
|
|
`bmi2`
|
|
|
|
|
`bti`
|
|
|
|
|
`bulk-memory`
|
|
|
|
|
`c`
|
|
|
|
|
`cache`
|
|
|
|
|
`cmpxchg16b`
|
|
|
|
|
`crc`
|
|
|
|
|
`crt-static`
|
|
|
|
|
`cssc`
|
|
|
|
|
`d`
|
|
|
|
|
`d32`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`deflate-conversion`
|
2024-12-01 18:19:20 +01:00
|
|
|
`dit`
|
2025-03-05 16:08:14 +08:00
|
|
|
`div32`
|
2024-12-01 18:19:20 +01:00
|
|
|
`doloop`
|
|
|
|
|
`dotprod`
|
|
|
|
|
`dpb`
|
|
|
|
|
`dpb2`
|
|
|
|
|
`dsp`
|
|
|
|
|
`dsp1e2`
|
|
|
|
|
`dspe60`
|
|
|
|
|
`e`
|
|
|
|
|
`e1`
|
|
|
|
|
`e2`
|
|
|
|
|
`ecv`
|
|
|
|
|
`edsp`
|
|
|
|
|
`elrw`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`enhanced-sort`
|
2024-12-01 18:19:20 +01:00
|
|
|
`ermsb`
|
|
|
|
|
`exception-handling`
|
|
|
|
|
`extended-const`
|
|
|
|
|
`f`
|
|
|
|
|
`f16c`
|
|
|
|
|
`f32mm`
|
|
|
|
|
`f64mm`
|
|
|
|
|
`faminmax`
|
|
|
|
|
`fcma`
|
|
|
|
|
`fdivdu`
|
|
|
|
|
`fhm`
|
|
|
|
|
`flagm`
|
|
|
|
|
`flagm2`
|
|
|
|
|
`float1e2`
|
|
|
|
|
`float1e3`
|
|
|
|
|
`float3e4`
|
|
|
|
|
`float7e60`
|
|
|
|
|
`floate1`
|
|
|
|
|
`fma`
|
|
|
|
|
`fp-armv8`
|
|
|
|
|
`fp16`
|
|
|
|
|
`fp64`
|
|
|
|
|
`fp8`
|
|
|
|
|
`fp8dot2`
|
|
|
|
|
`fp8dot4`
|
|
|
|
|
`fp8fma`
|
2024-11-16 10:26:46 +01:00
|
|
|
`fpregs`
|
2024-12-01 18:19:20 +01:00
|
|
|
`fpuv2_df`
|
|
|
|
|
`fpuv2_sf`
|
|
|
|
|
`fpuv3_df`
|
|
|
|
|
`fpuv3_hf`
|
|
|
|
|
`fpuv3_hi`
|
|
|
|
|
`fpuv3_sf`
|
|
|
|
|
`frecipe`
|
|
|
|
|
`frintts`
|
|
|
|
|
`fxsr`
|
|
|
|
|
`gfni`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`guarded-storage`
|
2024-12-01 18:19:20 +01:00
|
|
|
`hard-float`
|
|
|
|
|
`hard-float-abi`
|
|
|
|
|
`hard-tp`
|
|
|
|
|
`hbc`
|
|
|
|
|
`high-registers`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`high-word`
|
2024-12-01 18:19:20 +01:00
|
|
|
`hvx`
|
|
|
|
|
`hvx-length128b`
|
|
|
|
|
`hwdiv`
|
|
|
|
|
`i8mm`
|
2024-12-15 15:26:50 +09:00
|
|
|
`isa-68000`
|
|
|
|
|
`isa-68010`
|
|
|
|
|
`isa-68020`
|
|
|
|
|
`isa-68030`
|
|
|
|
|
`isa-68040`
|
|
|
|
|
`isa-68060`
|
|
|
|
|
`isa-68881`
|
|
|
|
|
`isa-68882`
|
2024-12-01 18:19:20 +01:00
|
|
|
`jsconv`
|
2024-12-27 11:47:34 +05:30
|
|
|
`kl`
|
2024-12-01 18:19:20 +01:00
|
|
|
`lahfsahf`
|
2025-03-05 16:08:14 +08:00
|
|
|
`lam-bh`
|
|
|
|
|
`lamcas`
|
2024-12-01 18:19:20 +01:00
|
|
|
`lasx`
|
|
|
|
|
`lbt`
|
2025-03-05 16:08:14 +08:00
|
|
|
`ld-seq-sa`
|
2024-12-01 18:19:20 +01:00
|
|
|
`leoncasa`
|
|
|
|
|
`lor`
|
|
|
|
|
`lse`
|
|
|
|
|
`lse128`
|
|
|
|
|
`lse2`
|
|
|
|
|
`lsx`
|
|
|
|
|
`lut`
|
|
|
|
|
`lvz`
|
|
|
|
|
`lzcnt`
|
|
|
|
|
`m`
|
|
|
|
|
`mclass`
|
|
|
|
|
`mops`
|
|
|
|
|
`movbe`
|
2025-03-04 20:08:28 +05:30
|
|
|
`movrs`
|
2024-12-01 18:19:20 +01:00
|
|
|
`mp`
|
|
|
|
|
`mp1e2`
|
|
|
|
|
`msa`
|
2025-03-02 03:03:52 +09:00
|
|
|
`msync`
|
2024-12-01 18:19:20 +01:00
|
|
|
`mte`
|
|
|
|
|
`multivalue`
|
|
|
|
|
`mutable-globals`
|
|
|
|
|
`neon`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`nnp-assist`
|
2024-12-01 18:19:20 +01:00
|
|
|
`nontrapping-fptoint`
|
|
|
|
|
`nvic`
|
|
|
|
|
`paca`
|
|
|
|
|
`pacg`
|
|
|
|
|
`pan`
|
|
|
|
|
`partword-atomics`
|
|
|
|
|
`pauth-lr`
|
|
|
|
|
`pclmulqdq`
|
|
|
|
|
`pmuv3`
|
|
|
|
|
`popcnt`
|
|
|
|
|
`power10-vector`
|
|
|
|
|
`power8-altivec`
|
2024-12-09 00:41:35 +05:30
|
|
|
`power8-crypto`
|
2024-12-01 18:19:20 +01:00
|
|
|
`power8-vector`
|
|
|
|
|
`power9-altivec`
|
|
|
|
|
`power9-vector`
|
|
|
|
|
`prfchw`
|
|
|
|
|
`quadword-atomics`
|
|
|
|
|
`rand`
|
|
|
|
|
`ras`
|
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|
|
`rclass`
|
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|
`rcpc`
|
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|
`rcpc2`
|
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|
`rcpc3`
|
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|
`rdm`
|
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|
`rdrand`
|
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|
`rdseed`
|
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|
|
|
`reference-types`
|
|
|
|
|
`relax`
|
|
|
|
|
`relaxed-simd`
|
|
|
|
|
`reserve-x18`
|
|
|
|
|
`rtm`
|
|
|
|
|
`sb`
|
2025-03-05 16:08:14 +08:00
|
|
|
`scq`
|
2024-12-01 18:19:20 +01:00
|
|
|
`sha`
|
|
|
|
|
`sha2`
|
|
|
|
|
`sha3`
|
|
|
|
|
`sha512`
|
|
|
|
|
`sign-ext`
|
|
|
|
|
`simd128`
|
|
|
|
|
`sm3`
|
|
|
|
|
`sm4`
|
|
|
|
|
`sme`
|
|
|
|
|
`sme-b16b16`
|
|
|
|
|
`sme-f16f16`
|
|
|
|
|
`sme-f64f64`
|
|
|
|
|
`sme-f8f16`
|
|
|
|
|
`sme-f8f32`
|
|
|
|
|
`sme-fa64`
|
|
|
|
|
`sme-i16i64`
|
|
|
|
|
`sme-lutv2`
|
|
|
|
|
`sme2`
|
|
|
|
|
`sme2p1`
|
2025-01-07 15:38:44 +01:00
|
|
|
`soft-float`
|
2024-12-01 18:19:20 +01:00
|
|
|
`spe`
|
|
|
|
|
`ssbs`
|
|
|
|
|
`sse`
|
|
|
|
|
`sse2`
|
|
|
|
|
`sse3`
|
|
|
|
|
`sse4.1`
|
|
|
|
|
`sse4.2`
|
|
|
|
|
`sse4a`
|
|
|
|
|
`ssse3`
|
|
|
|
|
`ssve-fp8dot2`
|
|
|
|
|
`ssve-fp8dot4`
|
|
|
|
|
`ssve-fp8fma`
|
|
|
|
|
`sve`
|
|
|
|
|
`sve-b16b16`
|
|
|
|
|
`sve2`
|
|
|
|
|
`sve2-aes`
|
|
|
|
|
`sve2-bitperm`
|
|
|
|
|
`sve2-sha3`
|
|
|
|
|
`sve2-sm4`
|
|
|
|
|
`sve2p1`
|
|
|
|
|
`tail-call`
|
|
|
|
|
`tbm`
|
|
|
|
|
`thumb-mode`
|
|
|
|
|
`thumb2`
|
|
|
|
|
`tme`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`transactional-execution`
|
2024-12-01 18:19:20 +01:00
|
|
|
`trust`
|
|
|
|
|
`trustzone`
|
|
|
|
|
`ual`
|
|
|
|
|
`unaligned-scalar-mem`
|
2025-03-20 19:47:57 +09:00
|
|
|
`unaligned-vector-mem`
|
2024-12-01 18:19:20 +01:00
|
|
|
`v`
|
|
|
|
|
`v5te`
|
|
|
|
|
`v6`
|
|
|
|
|
`v6k`
|
|
|
|
|
`v6t2`
|
|
|
|
|
`v7`
|
|
|
|
|
`v8`
|
|
|
|
|
`v8.1a`
|
|
|
|
|
`v8.2a`
|
|
|
|
|
`v8.3a`
|
|
|
|
|
`v8.4a`
|
|
|
|
|
`v8.5a`
|
|
|
|
|
`v8.6a`
|
|
|
|
|
`v8.7a`
|
|
|
|
|
`v8.8a`
|
|
|
|
|
`v8.9a`
|
|
|
|
|
`v8plus`
|
|
|
|
|
`v9`
|
|
|
|
|
`v9.1a`
|
|
|
|
|
`v9.2a`
|
|
|
|
|
`v9.3a`
|
|
|
|
|
`v9.4a`
|
|
|
|
|
`v9.5a`
|
|
|
|
|
`v9a`
|
|
|
|
|
`vaes`
|
|
|
|
|
`vdsp2e60f`
|
|
|
|
|
`vdspv1`
|
|
|
|
|
`vdspv2`
|
|
|
|
|
`vector`
|
add more s390x target features
The target feature names are, right now, based on the llvm target feature names. These mostly line up well with the names of [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) names. The linux kernel uses shorter, more cryptic names. (e.g. "vector" is `vx`). We can deviate from the llvm names, but the CPU vendor (IBM) does not appear to use e.g. `vx` for what they call `vector`.
There are a number of implied target features between the vector facilities (based on the [Facility Inidications](https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf#page=301) table):
- 129 The vector facility for z/Architecture is installed in the z/Architecture architectural mode.
- 134 The vector packed decimal facility is installed in the z/Architecture architectural mode. When bit 134 is one, bit 129 is also one.
- 135 The vector enhancements facility 1 is installed in the z/Architecture architectural mode. When bit 135 is one, bit 129 is also one.
- 148 The vector-enhancements facility 2 is installed in the z/Architecture architectural mode. When bit 148 is one, bits 129 and 135 are also one.
- 152 The vector-packed-decimal-enhancement facility 1 is installed in the z/Architecture architectural mode. When bit 152 is one, bits 129 and 134 are also one.
- 165 The neural-network-processing-assist facility is installed in the z/Architecture architectural mode. When bit 165 is one, bit 129 is also one.
- 192 The vector-packed-decimal-enhancement facility 2 is installed in the z/Architecture architectural mode. When bit 192 is one, bits 129, 134, and 152 are also one.
And then there are a number of facilities without any implied target features
- 45 The distinct-operands, fast-BCR-serialization, high-word, and population-count facilities, the interlocked-access facility 1, and the load/store-oncondition facility 1 are installed in the z/Architecture architectural mode.
- 73 The transactional-execution facility is installed in the z/Architecture architectural mode. Bit 49 is one when bit 73 is one.
- 133 The guarded-storage facility is installed in the z/Architecture architectural mode.
- 150 The enhanced-sort facility is installed in the z/Architecture architectural mode.
- 151 The DEFLATE-conversion facility is installed in the z/Architecture architectural mode.
The added target features are those that have ISA implications, can be queried at runtime, and have LLVM support. LLVM [defines more target features](https://github.com/llvm/llvm-project/blob/d49a2d2bc9c65c787bfa04ac8ece614da48a8cd5/llvm/lib/Target/SystemZ/SystemZFeatures.td), but I'm not sure those are useful. They can always be added later, and can already be set globally using `-Ctarget-feature`.
2025-01-17 14:57:18 +01:00
|
|
|
`vector-enhancements-1`
|
|
|
|
|
`vector-enhancements-2`
|
|
|
|
|
`vector-packed-decimal`
|
|
|
|
|
`vector-packed-decimal-enhancement`
|
|
|
|
|
`vector-packed-decimal-enhancement-2`
|
2024-12-01 18:19:20 +01:00
|
|
|
`vfp2`
|
|
|
|
|
`vfp3`
|
|
|
|
|
`vfp4`
|
|
|
|
|
`vh`
|
|
|
|
|
`virt`
|
|
|
|
|
`virtualization`
|
|
|
|
|
`vpclmulqdq`
|
|
|
|
|
`vsx`
|
|
|
|
|
`wfxt`
|
|
|
|
|
`wide-arithmetic`
|
2024-12-27 11:47:34 +05:30
|
|
|
`widekl`
|
2024-11-16 10:26:46 +01:00
|
|
|
`x87`
|
2024-12-01 18:19:20 +01:00
|
|
|
`xop`
|
|
|
|
|
`xsave`
|
|
|
|
|
`xsavec`
|
|
|
|
|
`xsaveopt`
|
|
|
|
|
`xsaves`
|
2025-02-22 16:15:14 +09:00
|
|
|
`za128rs`
|
|
|
|
|
`za64rs`
|
2024-12-01 18:19:20 +01:00
|
|
|
`zaamo`
|
|
|
|
|
`zabha`
|
2025-02-22 16:15:14 +09:00
|
|
|
`zacas`
|
2024-12-01 18:19:20 +01:00
|
|
|
`zalrsc`
|
2025-02-22 16:15:14 +09:00
|
|
|
`zama16b`
|
|
|
|
|
`zawrs`
|
2024-12-01 18:19:20 +01:00
|
|
|
`zba`
|
|
|
|
|
`zbb`
|
|
|
|
|
`zbc`
|
|
|
|
|
`zbkb`
|
|
|
|
|
`zbkc`
|
|
|
|
|
`zbkx`
|
|
|
|
|
`zbs`
|
|
|
|
|
`zdinx`
|
|
|
|
|
`zfh`
|
|
|
|
|
`zfhmin`
|
|
|
|
|
`zfinx`
|
|
|
|
|
`zhinx`
|
|
|
|
|
`zhinxmin`
|
2025-04-02 01:13:40 +00:00
|
|
|
`zicntr`
|
|
|
|
|
`zicsr`
|
|
|
|
|
`zifencei`
|
|
|
|
|
`zihintpause`
|
|
|
|
|
`zihpm`
|
2024-12-01 18:19:20 +01:00
|
|
|
`zk`
|
|
|
|
|
`zkn`
|
|
|
|
|
`zknd`
|
|
|
|
|
`zkne`
|
|
|
|
|
`zknh`
|
|
|
|
|
`zkr`
|
|
|
|
|
`zks`
|
|
|
|
|
`zksed`
|
2025-03-20 19:47:57 +09:00
|
|
|
`zksh`
|
|
|
|
|
`zkt`
|
|
|
|
|
`zvbb`
|
|
|
|
|
`zvbc`
|
|
|
|
|
`zve32f`
|
|
|
|
|
`zve32x`
|
|
|
|
|
`zve64d`
|
|
|
|
|
`zve64f`
|
|
|
|
|
`zve64x`
|
|
|
|
|
`zvfh`
|
|
|
|
|
`zvfhmin`
|
|
|
|
|
`zvkb`
|
|
|
|
|
`zvkg`
|
|
|
|
|
`zvkn`
|
|
|
|
|
`zvknc`
|
|
|
|
|
`zvkned`
|
|
|
|
|
`zvkng`
|
|
|
|
|
`zvknha`
|
|
|
|
|
`zvknhb`
|
|
|
|
|
`zvks`
|
|
|
|
|
`zvksc`
|
|
|
|
|
`zvksed`
|
|
|
|
|
`zvksg`
|
|
|
|
|
`zvksh`
|
|
|
|
|
`zvkt`
|
|
|
|
|
`zvl1024b`
|
|
|
|
|
`zvl128b`
|
|
|
|
|
`zvl16384b`
|
|
|
|
|
`zvl2048b`
|
|
|
|
|
`zvl256b`
|
|
|
|
|
`zvl32768b`
|
|
|
|
|
`zvl32b`
|
|
|
|
|
`zvl4096b`
|
|
|
|
|
`zvl512b`
|
|
|
|
|
`zvl64b`
|
|
|
|
|
`zvl65536b`, and `zvl8192b`
|
2024-12-01 18:19:20 +01:00
|
|
|
= note: see <https://doc.rust-lang.org/nightly/rustc/check-cfg.html> for more information about checking conditional configuration
|
|
|
|
|
= note: `#[warn(unexpected_cfgs)]` on by default
|
|
|
|
|
|
|
|
|
|
warning: 1 warning emitted
|
|
|
|
|
|