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rust/compiler/rustc_target/src/spec/thumbv7em_none_eabi.rs

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add +d16 and +fp-only-sp to thumbv7em-none-eabihf and documentation
2016-10-03 22:28:40 -05:00
// Targets the Cortex-M4 and Cortex-M7 processors (ARMv7E-M)
//
// This target assumes that the device doesn't have a FPU (Floating Point Unit) and lowers all the
// floating point operations to software routines (intrinsics).
//
// As such, this target uses the "soft" calling convention (ABI) where floating point values are
// passed to/from subroutines via general purpose registers (R0, R1, etc.).
//
// To opt-in to hardware accelerated floating point operations, you can use, for example,
// `-C target-feature=+vfp4` or `-C target-cpu=cortex-m4`.
rustc_target: Move `linker_flavor` from `Target` to `TargetOptions`
2020-10-08 22:22:28 +03:00
use crate::spec::{Target, TargetOptions};
add Thumbs to the compiler this commit adds 4 new target definitions to the compiler for easier cross compilation to ARM Cortex-M devices. - `thumbv6m-none-eabi` - For the Cortex-M0, Cortex-M0+ and Cortex-M1 - This architecture doesn't have hardware support (instructions) for atomics. Hence, the `Atomic*` structs are not available for this target. - `thumbv7m-none-eabi` - For the Cortex-M3 - `thumbv7em-none-eabi` - For the FPU-less variants of the Cortex-M4 and Cortex-M7 - On this target, all the floating point operations will be lowered software routines (intrinsics) - `thumbv7em-none-eabihf` - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU. - On this target, all the floating point operations will be lowered to hardware instructions No binary releases of standard crates, like `core`, are planned for these targets because Cargo, in the future, will compile e.g. the `core` crate on the fly as part of the `cargo build` process. In the meantime, you'll have to compile the `core` crate yourself. [Xargo] is the easiest way to do that as in handles the compilation of `core` automatically and can be used just like Cargo: `xargo build --target thumbv6m-none-eabi` is all that's needed. [Xargo]: https://crates.io/crates/xargo
2016-09-15 20:46:04 -05:00
rustc_target: Refactor away `TargetResult` Construction of a built-in target is always infallible now, so `TargetResult` is no longer necessary.
2020-10-05 15:37:55 +03:00
pub fn target() -> Target {
Target {
Replace every `String` in Target(Options) with `Cow<'static, str>`
2022-03-22 11:43:05 +01:00
llvm_target: "thumbv7em-none-eabi".into(),
Use integer literals for builtin target_pointer_width fields Also change target_pointer_width to pointer_width. Preparation for a subsequent type change of target_pointer_width to an integer together with a rename to pointer_width. On its own, this commit breaks the build. I don't like making build-breaking commits, but in this instance I believe that it makes review easier, as the "real" changes of this PR can be seen much more easily. Result of running: find compiler/rustc_target/src/spec/ -type f -exec sed -i -e 's/target_pointer_width: "\(.*\)"\..*,/pointer_width: \1,/g' {} \;
2020-10-14 18:08:12 +02:00
pointer_width: 32,
Replace every `String` in Target(Options) with `Cow<'static, str>`
2022-03-22 11:43:05 +01:00
data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
arch: "arm".into(),
add Thumbs to the compiler this commit adds 4 new target definitions to the compiler for easier cross compilation to ARM Cortex-M devices. - `thumbv6m-none-eabi` - For the Cortex-M0, Cortex-M0+ and Cortex-M1 - This architecture doesn't have hardware support (instructions) for atomics. Hence, the `Atomic*` structs are not available for this target. - `thumbv7m-none-eabi` - For the Cortex-M3 - `thumbv7em-none-eabi` - For the FPU-less variants of the Cortex-M4 and Cortex-M7 - On this target, all the floating point operations will be lowered software routines (intrinsics) - `thumbv7em-none-eabihf` - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU. - On this target, all the floating point operations will be lowered to hardware instructions No binary releases of standard crates, like `core`, are planned for these targets because Cargo, in the future, will compile e.g. the `core` crate on the fly as part of the `cargo build` process. In the meantime, you'll have to compile the `core` crate yourself. [Xargo] is the easiest way to do that as in handles the compilation of `core` automatically and can be used just like Cargo: `xargo build --target thumbv6m-none-eabi` is all that's needed. [Xargo]: https://crates.io/crates/xargo
2016-09-15 20:46:04 -05:00
Update targets to use target_abi All eabi targets have target_abi = "eabi". All eabihf targets have target_abi = "eabihf". armv6_unknown_freebsd and armv7_unknown_freebsd have target_abi = "eabihf". All abi64 targets have target_abi = "abi64". All ilp32 targets have target_abi = "ilp32". All softfloat targets have target_abi = "softfloat". All *-uwp-windows-* targets have target_abi = "uwp". All spe targets have target_abi = "spe". All macabi targets have target_abi = "macabi". aarch64-apple-ios-sim has target_abi = "sim". x86_64-fortanix-unknown-sgx has target_abi = "fortanix". x86_64-unknown-linux-gnux32 has target_abi = "x32". Add FIXME entries for targets for which existing values need to change once cfg_target_abi becomes stable. (All of them are tier 3 targets.) Add a test for target_abi in `--print cfg`.
2021-07-06 22:00:53 -07:00
options: TargetOptions {
Replace every `String` in Target(Options) with `Cow<'static, str>`
2022-03-22 11:43:05 +01:00
abi: "eabi".into(),
Update targets to use target_abi All eabi targets have target_abi = "eabi". All eabihf targets have target_abi = "eabihf". armv6_unknown_freebsd and armv7_unknown_freebsd have target_abi = "eabihf". All abi64 targets have target_abi = "abi64". All ilp32 targets have target_abi = "ilp32". All softfloat targets have target_abi = "softfloat". All *-uwp-windows-* targets have target_abi = "uwp". All spe targets have target_abi = "spe". All macabi targets have target_abi = "macabi". aarch64-apple-ios-sim has target_abi = "sim". x86_64-fortanix-unknown-sgx has target_abi = "fortanix". x86_64-unknown-linux-gnux32 has target_abi = "x32". Add FIXME entries for targets for which existing values need to change once cfg_target_abi becomes stable. (All of them are tier 3 targets.) Add a test for target_abi in `--print cfg`.
2021-07-06 22:00:53 -07:00
max_atomic_width: Some(32),
..super::thumb_base::opts()
},
rustc_target: Refactor away `TargetResult` Construction of a built-in target is always infallible now, so `TargetResult` is no longer necessary.
2020-10-05 15:37:55 +03:00
}
add Thumbs to the compiler this commit adds 4 new target definitions to the compiler for easier cross compilation to ARM Cortex-M devices. - `thumbv6m-none-eabi` - For the Cortex-M0, Cortex-M0+ and Cortex-M1 - This architecture doesn't have hardware support (instructions) for atomics. Hence, the `Atomic*` structs are not available for this target. - `thumbv7m-none-eabi` - For the Cortex-M3 - `thumbv7em-none-eabi` - For the FPU-less variants of the Cortex-M4 and Cortex-M7 - On this target, all the floating point operations will be lowered software routines (intrinsics) - `thumbv7em-none-eabihf` - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU. - On this target, all the floating point operations will be lowered to hardware instructions No binary releases of standard crates, like `core`, are planned for these targets because Cargo, in the future, will compile e.g. the `core` crate on the fly as part of the `cargo build` process. In the meantime, you'll have to compile the `core` crate yourself. [Xargo] is the easiest way to do that as in handles the compilation of `core` automatically and can be used just like Cargo: `xargo build --target thumbv6m-none-eabi` is all that's needed. [Xargo]: https://crates.io/crates/xargo
2016-09-15 20:46:04 -05:00
}
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