2020-01-22 11:24:31 +00:00
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use super::{InlineAsmArch, InlineAsmType};
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2020-06-21 15:34:18 +01:00
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use crate::spec::Target;
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2020-01-22 11:24:31 +00:00
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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def_reg_class! {
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RiscV RiscVInlineAsmRegClass {
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reg,
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freg,
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}
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}
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impl RiscVInlineAsmRegClass {
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pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
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&[]
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}
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2020-04-29 00:45:58 +01:00
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pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
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None
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}
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2020-01-22 11:24:31 +00:00
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pub fn suggest_modifier(
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self,
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_arch: InlineAsmArch,
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_ty: InlineAsmType,
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2020-04-29 00:45:58 +01:00
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) -> Option<(char, &'static str)> {
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2020-01-22 11:24:31 +00:00
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None
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}
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pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
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None
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}
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pub fn supported_types(
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self,
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arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<&'static str>)] {
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match self {
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Self::reg => {
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if arch == InlineAsmArch::RiscV64 {
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types! { _: I8, I16, I32, I64, F32, F64; }
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} else {
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types! { _: I8, I16, I32, F32; }
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}
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}
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Self::freg => types! { "f": F32; "d": F64; },
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}
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}
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}
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fn not_e(
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_arch: InlineAsmArch,
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mut has_feature: impl FnMut(&str) -> bool,
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2020-06-21 15:34:18 +01:00
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_target: &Target,
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2020-01-22 11:24:31 +00:00
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) -> Result<(), &'static str> {
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if has_feature("e") {
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Err("register can't be used with the `e` target feature")
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} else {
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Ok(())
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}
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}
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def_regs! {
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RiscV RiscVInlineAsmReg RiscVInlineAsmRegClass {
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x1: reg = ["x1", "ra"],
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x5: reg = ["x5", "t0"],
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x6: reg = ["x6", "t1"],
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x7: reg = ["x7", "t2"],
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x10: reg = ["x10", "a0"],
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x11: reg = ["x11", "a1"],
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x12: reg = ["x12", "a2"],
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x13: reg = ["x13", "a3"],
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x14: reg = ["x14", "a4"],
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x15: reg = ["x15", "a5"],
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x16: reg = ["x16", "a6"] % not_e,
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x17: reg = ["x17", "a7"] % not_e,
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x18: reg = ["x18", "s2"] % not_e,
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x19: reg = ["x19", "s3"] % not_e,
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x20: reg = ["x20", "s4"] % not_e,
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x21: reg = ["x21", "s5"] % not_e,
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x22: reg = ["x22", "s6"] % not_e,
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x23: reg = ["x23", "s7"] % not_e,
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x24: reg = ["x24", "s8"] % not_e,
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x25: reg = ["x25", "s9"] % not_e,
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x26: reg = ["x26", "s10"] % not_e,
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x27: reg = ["x27", "s11"] % not_e,
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x28: reg = ["x28", "t3"] % not_e,
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x29: reg = ["x29", "t4"] % not_e,
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x30: reg = ["x30", "t5"] % not_e,
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x31: reg = ["x31", "t6"] % not_e,
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f0: freg = ["f0", "ft0"],
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f1: freg = ["f1", "ft1"],
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f2: freg = ["f2", "ft2"],
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f3: freg = ["f3", "ft3"],
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f4: freg = ["f4", "ft4"],
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f5: freg = ["f5", "ft5"],
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f6: freg = ["f6", "ft6"],
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f7: freg = ["f7", "ft7"],
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f8: freg = ["f8", "fs0"],
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f9: freg = ["f9", "fs1"],
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f10: freg = ["f10", "fa0"],
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f11: freg = ["f11", "fa1"],
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f12: freg = ["f12", "fa2"],
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f13: freg = ["f13", "fa3"],
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f14: freg = ["f14", "fa4"],
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f15: freg = ["f15", "fa5"],
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f16: freg = ["f16", "fa6"],
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f17: freg = ["f17", "fa7"],
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f18: freg = ["f18", "fs2"],
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f19: freg = ["f19", "fs3"],
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f20: freg = ["f20", "fs4"],
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f21: freg = ["f21", "fs5"],
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f22: freg = ["f22", "fs6"],
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f23: freg = ["f23", "fs7"],
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f24: freg = ["f24", "fs8"],
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f25: freg = ["f25", "fs9"],
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f26: freg = ["f26", "fs10"],
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f27: freg = ["f27", "fs11"],
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f28: freg = ["f28", "ft8"],
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f29: freg = ["f29", "ft9"],
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f30: freg = ["f30", "ft10"],
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f31: freg = ["f31", "ft11"],
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2021-04-28 16:28:59 +01:00
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#error = ["x9", "s1"] =>
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"s1 is used internally by LLVM and cannot be used as an operand for inline asm",
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2020-03-19 07:41:43 +00:00
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#error = ["x8", "s0", "fp"] =>
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"the frame pointer cannot be used as an operand for inline asm",
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#error = ["x2", "sp"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["x3", "gp"] =>
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"the global pointer cannot be used as an operand for inline asm",
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#error = ["x4", "tp"] =>
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"the thread pointer cannot be used as an operand for inline asm" ,
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#error = ["x0", "zero"] =>
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"the zero register cannot be used as an operand for inline asm",
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2020-01-22 11:24:31 +00:00
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}
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}
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impl RiscVInlineAsmReg {
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pub fn emit(
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self,
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out: &mut dyn fmt::Write,
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_arch: InlineAsmArch,
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_modifier: Option<char>,
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) -> fmt::Result {
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out.write_str(self.name())
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}
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}
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