fb3c7e04c4
This includes both separate .md files, and documentation that was on the head of the .S source files. Retest everything as this was done, and fix a few easy things.
394 lines
6.6 KiB
NASM
394 lines
6.6 KiB
NASM
; TODO finish converting this to a text file that looks like the PDF...
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; ASSUMPTIONS:
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;
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; 1. The bottom 64K of memory is ram, and can be used for
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; scratch space by this module.
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;
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; 2. The system has sufficient free usable ram to copy the
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; initial GDT, IDT, and TSS
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; configuration data - must match with build definition
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CS_BASE EQU 0FFFF0000H
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; CS_BASE is the linear address of the segment STARTUP_CODE
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; - this is specified in the build language file
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RAM_START EQU 400H
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; RAM_START is the start of free, usable ram in the linear
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; memory space. The GDT, IDT, and initial TSS will be
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; copied above this space, and a small data segment will be
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; discarded at this linear address. The 32-bit word at
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; RAM_START will contain the linear address of the first
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; free byte above the copied tables - this may be useful if
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; a memory manager is used.
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TSS_INDEX EQU 10
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; TSS_INDEX is the index of the TSS of the first task to
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; run after startup
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ------------------------- STRUCTURES and EQU ---------------
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; structures for system data
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; TSS structure
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TASK_STATE STRUC
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link DW ?
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link_h DW ?
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ESP0 DD ?
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SS0 DW ?
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SS0_h DW ?
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ESP1 DD ?
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SS1 DW ?
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SS1_h DW ?
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ESP2 DD ?
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SS2 DW ?
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SS2_h DW ?
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CR3_reg DD ?
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EIP_reg DD ?
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EFLAGS_regDD ?
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EAX_reg DD ?
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ECX_reg DD ?
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EDX_reg DD ?
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EBX_reg DD ?
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ESP_reg DD ?
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EBP_reg DD ?
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ESI_reg DD ?
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EDI_reg DD ?
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ES_reg DW ?
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ES_h DW ?
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CS_reg DW ?
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CS_h DW ?
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SS_reg DW ?
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SS_h DW ?
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DS_reg DW ?
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DS_h DW ?
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FS_reg DW ?
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FS_h DW ?
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GS_reg DW ?
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GS_h DW ?
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LDT_reg DW ?
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LDT_h DW ?
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TRAP_reg DW ?
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IO_map_baseDW ?
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TASK_STATE ENDS
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; basic structure of a descriptor
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DESC STRUC
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lim_0_15 DW ?
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bas_0_15 DW ?
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bas_16_23 DB ?
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access DB ?
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gran DB ?
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bas_24_31 DB ?
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DESC ENDS
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; structure for use with LGDT and LIDT instructions
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TABLE_REG STRUC
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table_lim DW ?
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table_linearDD ?
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TABLE_REG
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ENDS
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; offset of GDT and IDT descriptors in builder generated GDT
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GDT_DESC_OFF
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EQU 1*SIZE(DESC)
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IDT_DESC_OFF
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EQU 2*SIZE(DESC)
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; equates for building temporary GDT in RAM
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LINEAR_SEL
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EQU
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1*SIZE (DESC)
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LINEAR_PROTO_LO
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EQU
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00000FFFFH ; LINEAR_ALIAS
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LINEAR_PROTO_HI
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EQU
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000CF9200H
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; Protection Enable Bit in CR0
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PE_BIT EQU 1B
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; ------------------------------------------------------------
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; ------------------------- DATA SEGMENT----------------------
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; Initially, this data segment starts at linear 0, according
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; to the processor’s power-up state.
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STARTUP_DATA
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SEGMENT RW
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free_mem_linear_base
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LABEL
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DWORD
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TEMP_GDT
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LABEL
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BYTE ; must be first in segment
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TEMP_GDT_NULL_DESC
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DESC
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<>
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TEMP_GDT_LINEAR_DESC DESC
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<>
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; scratch areas for LGDT and
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LIDT instructions
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TEMP_GDT_SCRATCH TABLE_REG
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<>
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APP_GDT_RAM
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TABLE_REG
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<>
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APP_IDT_RAM
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TABLE_REG
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<>
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; align end_data
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fill
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DW
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?
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; last thing in this segment - should be on a dword boundary
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end_data
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LABEL
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BYTE
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STARTUP_DATA
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ENDS
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; ------------------------------------------------------------
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; ------------------------- CODE SEGMENT----------------------
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STARTUP_CODE SEGMENT ER PUBLIC USE16
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; filled in by builder
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PUBLIC GDT_EPROM
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GDT_EPROM
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TABLE_REG
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<>
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; filled in by builder
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PUBLIC IDT_EPROM
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IDT_EPROM
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TABLE_REG
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<>
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; entry point into startup code - the bootstrap will vector
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; here with a near JMP generated by the builder.
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This
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; label must be in the top 64K of linear memory.
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PUBLIC
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STARTUP
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STARTUP:
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; DS,ES address the bottom 64K of flat linear memory
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ASSUME DS:STARTUP_DATA, ES:STARTUP_DATA
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; See Figure 9-4
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; load GDTR with temporary GDT
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LEA
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EBX,TEMP_GDT ; build the TEMP_GDT in low ram,
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MOV
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DWORD PTR [EBX],0
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; where we can address
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MOV
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DWORD PTR [EBX]+4,0
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MOV
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DWORD PTR [EBX]+8, LINEAR_PROTO_LO
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MOV
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DWORD PTR [EBX]+12, LINEAR_PROTO_HI
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MOV
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TEMP_GDT_scratch.table_linear,EBX
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MOV
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TEMP_GDT_scratch.table_lim,15
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DB 66H; execute a 32 bit LGDT
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LGDT
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TEMP_GDT_scratch
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; enter protected mode
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MOV
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EBX,CR0
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OR
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EBX,PE_BIT
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MOV
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CR0,EBX
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; clear prefetch queue
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JMP
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CLEAR_LABEL
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CLEAR_LABEL:
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; make DS and ES address 4G of linear memory
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MOV
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CX,LINEAR_SEL
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MOV
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DS,CX
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MOV
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ES,CX
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; do board specific initialization
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;
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;
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; ......
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;
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; See Figure 9-5
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; copy EPROM GDT to ram at:
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;
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RAM_START + size (STARTUP_DATA)
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MOV
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EAX,RAM_START
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ADD
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EAX,OFFSET (end_data)
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MOV
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EBX,RAM_START
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MOV
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ECX, CS_BASE
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ADD
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ECX, OFFSET (GDT_EPROM)
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MOV
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ESI, [ECX].table_linear
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MOV
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EDI,EAX
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MOVZX
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ECX, [ECX].table_lim
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MOV
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APP_GDT_ram[EBX].table_lim,CX
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INC
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ECX
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MOV
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EDX,EAX
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MOV
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APP_GDT_ram[EBX].table_linear,EAX
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ADD
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EAX,ECX
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REP MOVS
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BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
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; fixup
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GDT base in descriptor
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MOV
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ECX,EDX
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MOV
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[EDX].bas_0_15+GDT_DESC_OFF,CX
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ROR
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ECX,16
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; PAGE 4 TODO remove later.
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MOV
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[EDX].bas_16_23+GDT_DESC_OFF,CL
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[EDX].bas_24_31+GDT_DESC_OFF,CH
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; copy EPROM IDT to ram at:
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; RAM_START+size(STARTUP_DATA)+SIZE (EPROM GDT)
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MOV
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ECX, CS_BASE
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ADD
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ECX, OFFSET (IDT_EPROM)
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MOV
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ESI, [ECX].table_linear
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MOV
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EDI,EAX
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MOVZX
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ECX, [ECX].table_lim
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MOV
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APP_IDT_ram[EBX].table_lim,CX
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INC
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ECX
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MOV
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APP_IDT_ram[EBX].table_linear,EAX
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MOV
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EBX,EAX
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ADD
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EAX,ECX
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REP MOVS
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BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
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MOV
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ROR
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MOV
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MOV
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MOV
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LGDT
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LIDT
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REPMOV
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MOV
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MOV
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MOV
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MOV
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MOV
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ROL
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MOV
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MOV
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LSL
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INC
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MOV
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ADD
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MOVS
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MOV
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ROL
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MOV
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MOV
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ROL
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;save start
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MOV
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; fixup IDT pointer in GDT
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[EDX].bas_0_15+IDT_DESC_OFF,BX
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EBX,16
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[EDX].bas_16_23+IDT_DESC_OFF,BL
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[EDX].bas_24_31+IDT_DESC_OFF,BH
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; load GDTR and IDTR
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EBX,RAM_START
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DB
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66H
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; execute a 32 bit LGDT
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APP_GDT_ram[EBX]
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DB
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66H
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; execute a 32 bit LIDT
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APP_IDT_ram[EBX]
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; move the TSS
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EDI,EAX
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EBX,TSS_INDEX*SIZE(DESC)
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ECX,GDT_DESC_OFF ;build linear address for TSS
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GS,CX
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DH,GS:[EBX].bas_24_31
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DL,GS:[EBX].bas_16_23
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EDX,16
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DX,GS:[EBX].bas_0_15
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ESI,EDX
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ECX,EBX
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ECX
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EDX,EAX
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EAX,ECX
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BYTE PTR ES:[EDI],BYTE PTR DS:[ESI]
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; fixup TSS pointer
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GS:[EBX].bas_0_15,DX
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EDX,16
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GS:[EBX].bas_24_31,DH
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GS:[EBX].bas_16_23,DL
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EDX,16
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of free ram at linear location RAMSTART
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free_mem_linear_base+RAM_START,EAX
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;assume no LDT used in the initial task - if necessary,
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;code to move the LDT could be added, and should resemble
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;that used to move the TSS
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; load task register
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LTR
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BX
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; No task switch, only descriptor loading
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; See Figure 9-6
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; load minimal set of registers necessary to simulate task
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; switch
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MOV
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AX,[EDX].SS_reg
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; start loading registers
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MOV
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EDI,[EDX].ESP_reg
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MOV
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SS,AX
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MOV
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ESP,EDI
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; stack now valid
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PUSH
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DWORD PTR [EDX].EFLAGS_reg
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PUSH
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DWORD PTR [EDX].CS_reg
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PUSH
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DWORD PTR [EDX].EIP_reg
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MOV
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AX,[EDX].DS_reg
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MOV
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BX,[EDX].ES_reg
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MOV
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DS,AX
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; DS and ES no longer linear memory
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MOV
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ES,BX
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; simulate far jump to initial task
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IRETD
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STARTUP_CODE ENDS
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END STARTUP, DS:STARTUP_DATA, SS:STARTUP_DATA
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