104 lines
4.5 KiB
Markdown
104 lines
4.5 KiB
Markdown
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# PIC
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TODO add some examples.
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Programmable interrupt controller:
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- <http://wiki.osdev.org/PIC>
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- <http://www.jamesmolloy.co.uk/tutorial_html/5.-IRQs%20and%20the%20PIT.html>
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How it works:
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Hardware -> IRQ -> PIC -> Interrupt handler
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Each hardware has an IRQ, e.g. 0 for the PIT.
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When an IRQ activated (e.g. PIT sends a signal), the PIC decides:
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- whether or not it will call an interrupt handler. For example, without and EOI, further interrupts will not be generated.
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- which interrupt handler it will call. This can be modified by programming the PIT.x
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For example, Molloy shifts protected mode IRQs from interrupt 0 to 32, so that they won't conflict with the CPU defined exceptions in that area. <https://github.com/cirosantilli/jamesmolloy-kernel-development-tutorials/blob/d15a2dfb721008e2a3df132c8cda37c0e62ad826/5_irq/descriptor_tables.c#L72>
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The default IRQ assignment is shown at: <https://en.wikipedia.org/wiki/Interrupt_request_%28PC_architecture%29#x86_IRQs>
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Like other external circuits, the PIC is itself also programmed by `in` and `out` instructions.
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## EOI
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End of interrupt.
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We must tell the PIC that we are at the end.
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Otherwise new interrupts with equal or lower precedence don't fire again.
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<https://en.wikipedia.org/wiki/End_of_interrupt>
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## Plug and play
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TODO: how does plug and play configure IRQs?
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## APIC
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APIC vs PIC:
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- allows for multithreading
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- 24 IRQs instead of 15. The new top 8 are for PCI and deal better with conflicts.
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- has a millisecond timer built-in. Different from the HPET.
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## Linux
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### Shared IRQs
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It is possible to use a single IRQ for multiple hardware:
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<http://unix.stackexchange.com/questions/47306/how-does-the-linux-kernel-handle-shared-irqs>
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### /proc/interrupts
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PIC information can be found under:
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cat /proc/interrupts
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Sample output:
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CPU0 CPU1 CPU2 CPU3
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0: 19 0 0 0 IO-APIC-edge timer
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1: 1032 9717 745 811 IO-APIC-edge i8042
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8: 0 1 0 0 IO-APIC-edge rtc0
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9: 752 2027 603 895 IO-APIC-fasteoi acpi
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12: 139040 766443 108662 100894 IO-APIC-edge i8042
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16: 139 802 5766 10382 IO-APIC 16-fasteoi ehci_hcd:usb3, mmc0
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17: 216285 493484 25621 65079 IO-APIC 17-fasteoi rtl_pci
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23: 27 218 79 318 IO-APIC 23-fasteoi ehci_hcd:usb4
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25: 0 0 0 0 PCI-MSI-edge xhci_hcd
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26: 41510 101990 49473 124665 PCI-MSI-edge 0000:00:1f.2
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27: 10 2 4065 0 PCI-MSI-edge eth0
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28: 22 1 1 0 PCI-MSI-edge mei_me
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29: 65843 218345 46842 43270 PCI-MSI-edge i915
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30: 76 175 17 1 PCI-MSI-edge snd_hda_intel
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31: 12 16 5 7 PCI-MSI-edge nouveau
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NMI: 71 67 71 65 Non-maskable interrupts
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LOC: 1265066 702342 1396277 840420 Local timer interrupts
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SPU: 0 0 0 0 Spurious interrupts
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PMI: 71 67 71 65 Performance monitoring interrupts
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IWI: 0 0 0 0 IRQ work interrupts
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RTR: 0 0 0 0 APIC ICR read retries
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RES: 180487 200186 197582 204727 Rescheduling interrupts
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CAL: 2570 885 1391 1252 Function call interrupts
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TLB: 60853 64789 54844 73507 TLB shootdowns
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TRM: 0 0 0 0 Thermal event interrupts
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THR: 0 0 0 0 Threshold APIC interrupts
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MCE: 0 0 0 0 Machine check exceptions
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MCP: 29 29 29 29 Machine check polls
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HYP: 0 0 0 0 Hypervisor callback interrupts
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ERR: 0
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MIS: 0
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- timer: PIT
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- i8042: keyboard
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- fasteoi vs edge: <http://stackoverflow.com/questions/7005331/difference-between-io-apic-fasteoi-and-io-apic-edge>
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- PCI-MSI-edge: <http://stackoverflow.com/questions/10894702/diff-between-io-apic-level-and-pci-msi-x>
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- EHCI http://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-specification.html
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